atsamd21j/sercom0/i2cs/
intenset.rs

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1#[doc = "Register `INTENSET` reader"]
2pub type R = crate::R<IntensetSpec>;
3#[doc = "Register `INTENSET` writer"]
4pub type W = crate::W<IntensetSpec>;
5#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"]
6pub type PrecR = crate::BitReader;
7#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"]
8pub type PrecW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"]
10pub type AmatchR = crate::BitReader;
11#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"]
12pub type AmatchW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DRDY` reader - Data Interrupt Enable"]
14pub type DrdyR = crate::BitReader;
15#[doc = "Field `DRDY` writer - Data Interrupt Enable"]
16pub type DrdyW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"]
18pub type ErrorR = crate::BitReader;
19#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"]
20pub type ErrorW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Stop Received Interrupt Enable"]
23    #[inline(always)]
24    pub fn prec(&self) -> PrecR {
25        PrecR::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Address Match Interrupt Enable"]
28    #[inline(always)]
29    pub fn amatch(&self) -> AmatchR {
30        AmatchR::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Data Interrupt Enable"]
33    #[inline(always)]
34    pub fn drdy(&self) -> DrdyR {
35        DrdyR::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
38    #[inline(always)]
39    pub fn error(&self) -> ErrorR {
40        ErrorR::new(((self.bits >> 7) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Stop Received Interrupt Enable"]
45    #[inline(always)]
46    #[must_use]
47    pub fn prec(&mut self) -> PrecW<IntensetSpec> {
48        PrecW::new(self, 0)
49    }
50    #[doc = "Bit 1 - Address Match Interrupt Enable"]
51    #[inline(always)]
52    #[must_use]
53    pub fn amatch(&mut self) -> AmatchW<IntensetSpec> {
54        AmatchW::new(self, 1)
55    }
56    #[doc = "Bit 2 - Data Interrupt Enable"]
57    #[inline(always)]
58    #[must_use]
59    pub fn drdy(&mut self) -> DrdyW<IntensetSpec> {
60        DrdyW::new(self, 2)
61    }
62    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn error(&mut self) -> ErrorW<IntensetSpec> {
66        ErrorW::new(self, 7)
67    }
68}
69#[doc = "I2CS Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct IntensetSpec;
71impl crate::RegisterSpec for IntensetSpec {
72    type Ux = u8;
73}
74#[doc = "`read()` method returns [`intenset::R`](R) reader structure"]
75impl crate::Readable for IntensetSpec {}
76#[doc = "`write(|w| ..)` method takes [`intenset::W`](W) writer structure"]
77impl crate::Writable for IntensetSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
81}
82#[doc = "`reset()` method sets INTENSET to value 0"]
83impl crate::Resettable for IntensetSpec {
84    const RESET_VALUE: u8 = 0;
85}
atsamd21j/sercom0/i2cs/intenset.rs

atsamd21j/sercom0/i2cs/
intenset.rs
