atsamd21j/evsys/
intenclr.rs

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1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"]
6pub type Ovr0R = crate::BitReader;
7#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"]
8pub type Ovr0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"]
10pub type Ovr1R = crate::BitReader;
11#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"]
12pub type Ovr1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"]
14pub type Ovr2R = crate::BitReader;
15#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"]
16pub type Ovr2W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"]
18pub type Ovr3R = crate::BitReader;
19#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"]
20pub type Ovr3W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"]
22pub type Ovr4R = crate::BitReader;
23#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"]
24pub type Ovr4W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"]
26pub type Ovr5R = crate::BitReader;
27#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"]
28pub type Ovr5W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"]
30pub type Ovr6R = crate::BitReader;
31#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"]
32pub type Ovr6W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"]
34pub type Ovr7R = crate::BitReader;
35#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"]
36pub type Ovr7W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"]
38pub type Evd0R = crate::BitReader;
39#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"]
40pub type Evd0W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"]
42pub type Evd1R = crate::BitReader;
43#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"]
44pub type Evd1W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"]
46pub type Evd2R = crate::BitReader;
47#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"]
48pub type Evd2W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"]
50pub type Evd3R = crate::BitReader;
51#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"]
52pub type Evd3W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"]
54pub type Evd4R = crate::BitReader;
55#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"]
56pub type Evd4W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"]
58pub type Evd5R = crate::BitReader;
59#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"]
60pub type Evd5W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"]
62pub type Evd6R = crate::BitReader;
63#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"]
64pub type Evd6W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"]
66pub type Evd7R = crate::BitReader;
67#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"]
68pub type Evd7W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `OVR8` reader - Channel 8 Overrun Interrupt Enable"]
70pub type Ovr8R = crate::BitReader;
71#[doc = "Field `OVR8` writer - Channel 8 Overrun Interrupt Enable"]
72pub type Ovr8W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `OVR9` reader - Channel 9 Overrun Interrupt Enable"]
74pub type Ovr9R = crate::BitReader;
75#[doc = "Field `OVR9` writer - Channel 9 Overrun Interrupt Enable"]
76pub type Ovr9W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `OVR10` reader - Channel 10 Overrun Interrupt Enable"]
78pub type Ovr10R = crate::BitReader;
79#[doc = "Field `OVR10` writer - Channel 10 Overrun Interrupt Enable"]
80pub type Ovr10W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `OVR11` reader - Channel 11 Overrun Interrupt Enable"]
82pub type Ovr11R = crate::BitReader;
83#[doc = "Field `OVR11` writer - Channel 11 Overrun Interrupt Enable"]
84pub type Ovr11W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `EVD8` reader - Channel 8 Event Detection Interrupt Enable"]
86pub type Evd8R = crate::BitReader;
87#[doc = "Field `EVD8` writer - Channel 8 Event Detection Interrupt Enable"]
88pub type Evd8W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `EVD9` reader - Channel 9 Event Detection Interrupt Enable"]
90pub type Evd9R = crate::BitReader;
91#[doc = "Field `EVD9` writer - Channel 9 Event Detection Interrupt Enable"]
92pub type Evd9W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `EVD10` reader - Channel 10 Event Detection Interrupt Enable"]
94pub type Evd10R = crate::BitReader;
95#[doc = "Field `EVD10` writer - Channel 10 Event Detection Interrupt Enable"]
96pub type Evd10W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `EVD11` reader - Channel 11 Event Detection Interrupt Enable"]
98pub type Evd11R = crate::BitReader;
99#[doc = "Field `EVD11` writer - Channel 11 Event Detection Interrupt Enable"]
100pub type Evd11W<'a, REG> = crate::BitWriter<'a, REG>;
101impl R {
102    #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"]
103    #[inline(always)]
104    pub fn ovr0(&self) -> Ovr0R {
105        Ovr0R::new((self.bits & 1) != 0)
106    }
107    #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"]
108    #[inline(always)]
109    pub fn ovr1(&self) -> Ovr1R {
110        Ovr1R::new(((self.bits >> 1) & 1) != 0)
111    }
112    #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"]
113    #[inline(always)]
114    pub fn ovr2(&self) -> Ovr2R {
115        Ovr2R::new(((self.bits >> 2) & 1) != 0)
116    }
117    #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"]
118    #[inline(always)]
119    pub fn ovr3(&self) -> Ovr3R {
120        Ovr3R::new(((self.bits >> 3) & 1) != 0)
121    }
122    #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"]
123    #[inline(always)]
124    pub fn ovr4(&self) -> Ovr4R {
125        Ovr4R::new(((self.bits >> 4) & 1) != 0)
126    }
127    #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"]
128    #[inline(always)]
129    pub fn ovr5(&self) -> Ovr5R {
130        Ovr5R::new(((self.bits >> 5) & 1) != 0)
131    }
132    #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"]
133    #[inline(always)]
134    pub fn ovr6(&self) -> Ovr6R {
135        Ovr6R::new(((self.bits >> 6) & 1) != 0)
136    }
137    #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"]
138    #[inline(always)]
139    pub fn ovr7(&self) -> Ovr7R {
140        Ovr7R::new(((self.bits >> 7) & 1) != 0)
141    }
142    #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"]
143    #[inline(always)]
144    pub fn evd0(&self) -> Evd0R {
145        Evd0R::new(((self.bits >> 8) & 1) != 0)
146    }
147    #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"]
148    #[inline(always)]
149    pub fn evd1(&self) -> Evd1R {
150        Evd1R::new(((self.bits >> 9) & 1) != 0)
151    }
152    #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"]
153    #[inline(always)]
154    pub fn evd2(&self) -> Evd2R {
155        Evd2R::new(((self.bits >> 10) & 1) != 0)
156    }
157    #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"]
158    #[inline(always)]
159    pub fn evd3(&self) -> Evd3R {
160        Evd3R::new(((self.bits >> 11) & 1) != 0)
161    }
162    #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"]
163    #[inline(always)]
164    pub fn evd4(&self) -> Evd4R {
165        Evd4R::new(((self.bits >> 12) & 1) != 0)
166    }
167    #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"]
168    #[inline(always)]
169    pub fn evd5(&self) -> Evd5R {
170        Evd5R::new(((self.bits >> 13) & 1) != 0)
171    }
172    #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"]
173    #[inline(always)]
174    pub fn evd6(&self) -> Evd6R {
175        Evd6R::new(((self.bits >> 14) & 1) != 0)
176    }
177    #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"]
178    #[inline(always)]
179    pub fn evd7(&self) -> Evd7R {
180        Evd7R::new(((self.bits >> 15) & 1) != 0)
181    }
182    #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"]
183    #[inline(always)]
184    pub fn ovr8(&self) -> Ovr8R {
185        Ovr8R::new(((self.bits >> 16) & 1) != 0)
186    }
187    #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"]
188    #[inline(always)]
189    pub fn ovr9(&self) -> Ovr9R {
190        Ovr9R::new(((self.bits >> 17) & 1) != 0)
191    }
192    #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"]
193    #[inline(always)]
194    pub fn ovr10(&self) -> Ovr10R {
195        Ovr10R::new(((self.bits >> 18) & 1) != 0)
196    }
197    #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"]
198    #[inline(always)]
199    pub fn ovr11(&self) -> Ovr11R {
200        Ovr11R::new(((self.bits >> 19) & 1) != 0)
201    }
202    #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"]
203    #[inline(always)]
204    pub fn evd8(&self) -> Evd8R {
205        Evd8R::new(((self.bits >> 24) & 1) != 0)
206    }
207    #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"]
208    #[inline(always)]
209    pub fn evd9(&self) -> Evd9R {
210        Evd9R::new(((self.bits >> 25) & 1) != 0)
211    }
212    #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"]
213    #[inline(always)]
214    pub fn evd10(&self) -> Evd10R {
215        Evd10R::new(((self.bits >> 26) & 1) != 0)
216    }
217    #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"]
218    #[inline(always)]
219    pub fn evd11(&self) -> Evd11R {
220        Evd11R::new(((self.bits >> 27) & 1) != 0)
221    }
222}
223impl W {
224    #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"]
225    #[inline(always)]
226    #[must_use]
227    pub fn ovr0(&mut self) -> Ovr0W<IntenclrSpec> {
228        Ovr0W::new(self, 0)
229    }
230    #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"]
231    #[inline(always)]
232    #[must_use]
233    pub fn ovr1(&mut self) -> Ovr1W<IntenclrSpec> {
234        Ovr1W::new(self, 1)
235    }
236    #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"]
237    #[inline(always)]
238    #[must_use]
239    pub fn ovr2(&mut self) -> Ovr2W<IntenclrSpec> {
240        Ovr2W::new(self, 2)
241    }
242    #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"]
243    #[inline(always)]
244    #[must_use]
245    pub fn ovr3(&mut self) -> Ovr3W<IntenclrSpec> {
246        Ovr3W::new(self, 3)
247    }
248    #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"]
249    #[inline(always)]
250    #[must_use]
251    pub fn ovr4(&mut self) -> Ovr4W<IntenclrSpec> {
252        Ovr4W::new(self, 4)
253    }
254    #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"]
255    #[inline(always)]
256    #[must_use]
257    pub fn ovr5(&mut self) -> Ovr5W<IntenclrSpec> {
258        Ovr5W::new(self, 5)
259    }
260    #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"]
261    #[inline(always)]
262    #[must_use]
263    pub fn ovr6(&mut self) -> Ovr6W<IntenclrSpec> {
264        Ovr6W::new(self, 6)
265    }
266    #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"]
267    #[inline(always)]
268    #[must_use]
269    pub fn ovr7(&mut self) -> Ovr7W<IntenclrSpec> {
270        Ovr7W::new(self, 7)
271    }
272    #[doc = "Bit 8 - Channel 0 Event Detection Interrupt Enable"]
273    #[inline(always)]
274    #[must_use]
275    pub fn evd0(&mut self) -> Evd0W<IntenclrSpec> {
276        Evd0W::new(self, 8)
277    }
278    #[doc = "Bit 9 - Channel 1 Event Detection Interrupt Enable"]
279    #[inline(always)]
280    #[must_use]
281    pub fn evd1(&mut self) -> Evd1W<IntenclrSpec> {
282        Evd1W::new(self, 9)
283    }
284    #[doc = "Bit 10 - Channel 2 Event Detection Interrupt Enable"]
285    #[inline(always)]
286    #[must_use]
287    pub fn evd2(&mut self) -> Evd2W<IntenclrSpec> {
288        Evd2W::new(self, 10)
289    }
290    #[doc = "Bit 11 - Channel 3 Event Detection Interrupt Enable"]
291    #[inline(always)]
292    #[must_use]
293    pub fn evd3(&mut self) -> Evd3W<IntenclrSpec> {
294        Evd3W::new(self, 11)
295    }
296    #[doc = "Bit 12 - Channel 4 Event Detection Interrupt Enable"]
297    #[inline(always)]
298    #[must_use]
299    pub fn evd4(&mut self) -> Evd4W<IntenclrSpec> {
300        Evd4W::new(self, 12)
301    }
302    #[doc = "Bit 13 - Channel 5 Event Detection Interrupt Enable"]
303    #[inline(always)]
304    #[must_use]
305    pub fn evd5(&mut self) -> Evd5W<IntenclrSpec> {
306        Evd5W::new(self, 13)
307    }
308    #[doc = "Bit 14 - Channel 6 Event Detection Interrupt Enable"]
309    #[inline(always)]
310    #[must_use]
311    pub fn evd6(&mut self) -> Evd6W<IntenclrSpec> {
312        Evd6W::new(self, 14)
313    }
314    #[doc = "Bit 15 - Channel 7 Event Detection Interrupt Enable"]
315    #[inline(always)]
316    #[must_use]
317    pub fn evd7(&mut self) -> Evd7W<IntenclrSpec> {
318        Evd7W::new(self, 15)
319    }
320    #[doc = "Bit 16 - Channel 8 Overrun Interrupt Enable"]
321    #[inline(always)]
322    #[must_use]
323    pub fn ovr8(&mut self) -> Ovr8W<IntenclrSpec> {
324        Ovr8W::new(self, 16)
325    }
326    #[doc = "Bit 17 - Channel 9 Overrun Interrupt Enable"]
327    #[inline(always)]
328    #[must_use]
329    pub fn ovr9(&mut self) -> Ovr9W<IntenclrSpec> {
330        Ovr9W::new(self, 17)
331    }
332    #[doc = "Bit 18 - Channel 10 Overrun Interrupt Enable"]
333    #[inline(always)]
334    #[must_use]
335    pub fn ovr10(&mut self) -> Ovr10W<IntenclrSpec> {
336        Ovr10W::new(self, 18)
337    }
338    #[doc = "Bit 19 - Channel 11 Overrun Interrupt Enable"]
339    #[inline(always)]
340    #[must_use]
341    pub fn ovr11(&mut self) -> Ovr11W<IntenclrSpec> {
342        Ovr11W::new(self, 19)
343    }
344    #[doc = "Bit 24 - Channel 8 Event Detection Interrupt Enable"]
345    #[inline(always)]
346    #[must_use]
347    pub fn evd8(&mut self) -> Evd8W<IntenclrSpec> {
348        Evd8W::new(self, 24)
349    }
350    #[doc = "Bit 25 - Channel 9 Event Detection Interrupt Enable"]
351    #[inline(always)]
352    #[must_use]
353    pub fn evd9(&mut self) -> Evd9W<IntenclrSpec> {
354        Evd9W::new(self, 25)
355    }
356    #[doc = "Bit 26 - Channel 10 Event Detection Interrupt Enable"]
357    #[inline(always)]
358    #[must_use]
359    pub fn evd10(&mut self) -> Evd10W<IntenclrSpec> {
360        Evd10W::new(self, 26)
361    }
362    #[doc = "Bit 27 - Channel 11 Event Detection Interrupt Enable"]
363    #[inline(always)]
364    #[must_use]
365    pub fn evd11(&mut self) -> Evd11W<IntenclrSpec> {
366        Evd11W::new(self, 27)
367    }
368}
369#[doc = "Interrupt Enable Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
370pub struct IntenclrSpec;
371impl crate::RegisterSpec for IntenclrSpec {
372    type Ux = u32;
373}
374#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
375impl crate::Readable for IntenclrSpec {}
376#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
377impl crate::Writable for IntenclrSpec {
378    type Safety = crate::Unsafe;
379    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
380    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
381}
382#[doc = "`reset()` method sets INTENCLR to value 0"]
383impl crate::Resettable for IntenclrSpec {
384    const RESET_VALUE: u32 = 0;
385}
atsamd21j/evsys/intenclr.rs

atsamd21j/evsys/
intenclr.rs
