atsamd11d/tcc0/
ctrla.rs

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1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Enhanced Resolution\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Resolutionselect {
17    #[doc = "0: Dithering is disabled"]
18    None = 0,
19    #[doc = "1: Dithering is done every 16 PWM frames"]
20    Dith4 = 1,
21    #[doc = "2: Dithering is done every 32 PWM frames"]
22    Dith5 = 2,
23    #[doc = "3: Dithering is done every 64 PWM frames"]
24    Dith6 = 3,
25}
26impl From<Resolutionselect> for u8 {
27    #[inline(always)]
28    fn from(variant: Resolutionselect) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for Resolutionselect {
33    type Ux = u8;
34}
35impl crate::IsEnum for Resolutionselect {}
36#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"]
37pub type ResolutionR = crate::FieldReader<Resolutionselect>;
38impl ResolutionR {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub const fn variant(&self) -> Resolutionselect {
42        match self.bits {
43            0 => Resolutionselect::None,
44            1 => Resolutionselect::Dith4,
45            2 => Resolutionselect::Dith5,
46            3 => Resolutionselect::Dith6,
47            _ => unreachable!(),
48        }
49    }
50    #[doc = "Dithering is disabled"]
51    #[inline(always)]
52    pub fn is_none(&self) -> bool {
53        *self == Resolutionselect::None
54    }
55    #[doc = "Dithering is done every 16 PWM frames"]
56    #[inline(always)]
57    pub fn is_dith4(&self) -> bool {
58        *self == Resolutionselect::Dith4
59    }
60    #[doc = "Dithering is done every 32 PWM frames"]
61    #[inline(always)]
62    pub fn is_dith5(&self) -> bool {
63        *self == Resolutionselect::Dith5
64    }
65    #[doc = "Dithering is done every 64 PWM frames"]
66    #[inline(always)]
67    pub fn is_dith6(&self) -> bool {
68        *self == Resolutionselect::Dith6
69    }
70}
71#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"]
72pub type ResolutionW<'a, REG> = crate::FieldWriter<'a, REG, 2, Resolutionselect, crate::Safe>;
73impl<'a, REG> ResolutionW<'a, REG>
74where
75    REG: crate::Writable + crate::RegisterSpec,
76    REG::Ux: From<u8>,
77{
78    #[doc = "Dithering is disabled"]
79    #[inline(always)]
80    pub fn none(self) -> &'a mut crate::W<REG> {
81        self.variant(Resolutionselect::None)
82    }
83    #[doc = "Dithering is done every 16 PWM frames"]
84    #[inline(always)]
85    pub fn dith4(self) -> &'a mut crate::W<REG> {
86        self.variant(Resolutionselect::Dith4)
87    }
88    #[doc = "Dithering is done every 32 PWM frames"]
89    #[inline(always)]
90    pub fn dith5(self) -> &'a mut crate::W<REG> {
91        self.variant(Resolutionselect::Dith5)
92    }
93    #[doc = "Dithering is done every 64 PWM frames"]
94    #[inline(always)]
95    pub fn dith6(self) -> &'a mut crate::W<REG> {
96        self.variant(Resolutionselect::Dith6)
97    }
98}
99#[doc = "Prescaler\n\nValue on reset: 0"]
100#[derive(Clone, Copy, Debug, PartialEq, Eq)]
101#[repr(u8)]
102pub enum Prescalerselect {
103    #[doc = "0: No division"]
104    Div1 = 0,
105    #[doc = "1: Divide by 2"]
106    Div2 = 1,
107    #[doc = "2: Divide by 4"]
108    Div4 = 2,
109    #[doc = "3: Divide by 8"]
110    Div8 = 3,
111    #[doc = "4: Divide by 16"]
112    Div16 = 4,
113    #[doc = "5: Divide by 64"]
114    Div64 = 5,
115    #[doc = "6: Divide by 256"]
116    Div256 = 6,
117    #[doc = "7: Divide by 1024"]
118    Div1024 = 7,
119}
120impl From<Prescalerselect> for u8 {
121    #[inline(always)]
122    fn from(variant: Prescalerselect) -> Self {
123        variant as _
124    }
125}
126impl crate::FieldSpec for Prescalerselect {
127    type Ux = u8;
128}
129impl crate::IsEnum for Prescalerselect {}
130#[doc = "Field `PRESCALER` reader - Prescaler"]
131pub type PrescalerR = crate::FieldReader<Prescalerselect>;
132impl PrescalerR {
133    #[doc = "Get enumerated values variant"]
134    #[inline(always)]
135    pub const fn variant(&self) -> Prescalerselect {
136        match self.bits {
137            0 => Prescalerselect::Div1,
138            1 => Prescalerselect::Div2,
139            2 => Prescalerselect::Div4,
140            3 => Prescalerselect::Div8,
141            4 => Prescalerselect::Div16,
142            5 => Prescalerselect::Div64,
143            6 => Prescalerselect::Div256,
144            7 => Prescalerselect::Div1024,
145            _ => unreachable!(),
146        }
147    }
148    #[doc = "No division"]
149    #[inline(always)]
150    pub fn is_div1(&self) -> bool {
151        *self == Prescalerselect::Div1
152    }
153    #[doc = "Divide by 2"]
154    #[inline(always)]
155    pub fn is_div2(&self) -> bool {
156        *self == Prescalerselect::Div2
157    }
158    #[doc = "Divide by 4"]
159    #[inline(always)]
160    pub fn is_div4(&self) -> bool {
161        *self == Prescalerselect::Div4
162    }
163    #[doc = "Divide by 8"]
164    #[inline(always)]
165    pub fn is_div8(&self) -> bool {
166        *self == Prescalerselect::Div8
167    }
168    #[doc = "Divide by 16"]
169    #[inline(always)]
170    pub fn is_div16(&self) -> bool {
171        *self == Prescalerselect::Div16
172    }
173    #[doc = "Divide by 64"]
174    #[inline(always)]
175    pub fn is_div64(&self) -> bool {
176        *self == Prescalerselect::Div64
177    }
178    #[doc = "Divide by 256"]
179    #[inline(always)]
180    pub fn is_div256(&self) -> bool {
181        *self == Prescalerselect::Div256
182    }
183    #[doc = "Divide by 1024"]
184    #[inline(always)]
185    pub fn is_div1024(&self) -> bool {
186        *self == Prescalerselect::Div1024
187    }
188}
189#[doc = "Field `PRESCALER` writer - Prescaler"]
190pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescalerselect, crate::Safe>;
191impl<'a, REG> PrescalerW<'a, REG>
192where
193    REG: crate::Writable + crate::RegisterSpec,
194    REG::Ux: From<u8>,
195{
196    #[doc = "No division"]
197    #[inline(always)]
198    pub fn div1(self) -> &'a mut crate::W<REG> {
199        self.variant(Prescalerselect::Div1)
200    }
201    #[doc = "Divide by 2"]
202    #[inline(always)]
203    pub fn div2(self) -> &'a mut crate::W<REG> {
204        self.variant(Prescalerselect::Div2)
205    }
206    #[doc = "Divide by 4"]
207    #[inline(always)]
208    pub fn div4(self) -> &'a mut crate::W<REG> {
209        self.variant(Prescalerselect::Div4)
210    }
211    #[doc = "Divide by 8"]
212    #[inline(always)]
213    pub fn div8(self) -> &'a mut crate::W<REG> {
214        self.variant(Prescalerselect::Div8)
215    }
216    #[doc = "Divide by 16"]
217    #[inline(always)]
218    pub fn div16(self) -> &'a mut crate::W<REG> {
219        self.variant(Prescalerselect::Div16)
220    }
221    #[doc = "Divide by 64"]
222    #[inline(always)]
223    pub fn div64(self) -> &'a mut crate::W<REG> {
224        self.variant(Prescalerselect::Div64)
225    }
226    #[doc = "Divide by 256"]
227    #[inline(always)]
228    pub fn div256(self) -> &'a mut crate::W<REG> {
229        self.variant(Prescalerselect::Div256)
230    }
231    #[doc = "Divide by 1024"]
232    #[inline(always)]
233    pub fn div1024(self) -> &'a mut crate::W<REG> {
234        self.variant(Prescalerselect::Div1024)
235    }
236}
237#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
238pub type RunstdbyR = crate::BitReader;
239#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
240pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
241#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"]
242#[derive(Clone, Copy, Debug, PartialEq, Eq)]
243#[repr(u8)]
244pub enum Prescsyncselect {
245    #[doc = "0: Reload or reset counter on next GCLK"]
246    Gclk = 0,
247    #[doc = "1: Reload or reset counter on next prescaler clock"]
248    Presc = 1,
249    #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"]
250    Resync = 2,
251}
252impl From<Prescsyncselect> for u8 {
253    #[inline(always)]
254    fn from(variant: Prescsyncselect) -> Self {
255        variant as _
256    }
257}
258impl crate::FieldSpec for Prescsyncselect {
259    type Ux = u8;
260}
261impl crate::IsEnum for Prescsyncselect {}
262#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"]
263pub type PrescsyncR = crate::FieldReader<Prescsyncselect>;
264impl PrescsyncR {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub const fn variant(&self) -> Option<Prescsyncselect> {
268        match self.bits {
269            0 => Some(Prescsyncselect::Gclk),
270            1 => Some(Prescsyncselect::Presc),
271            2 => Some(Prescsyncselect::Resync),
272            _ => None,
273        }
274    }
275    #[doc = "Reload or reset counter on next GCLK"]
276    #[inline(always)]
277    pub fn is_gclk(&self) -> bool {
278        *self == Prescsyncselect::Gclk
279    }
280    #[doc = "Reload or reset counter on next prescaler clock"]
281    #[inline(always)]
282    pub fn is_presc(&self) -> bool {
283        *self == Prescsyncselect::Presc
284    }
285    #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"]
286    #[inline(always)]
287    pub fn is_resync(&self) -> bool {
288        *self == Prescsyncselect::Resync
289    }
290}
291#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"]
292pub type PrescsyncW<'a, REG> = crate::FieldWriter<'a, REG, 2, Prescsyncselect>;
293impl<'a, REG> PrescsyncW<'a, REG>
294where
295    REG: crate::Writable + crate::RegisterSpec,
296    REG::Ux: From<u8>,
297{
298    #[doc = "Reload or reset counter on next GCLK"]
299    #[inline(always)]
300    pub fn gclk(self) -> &'a mut crate::W<REG> {
301        self.variant(Prescsyncselect::Gclk)
302    }
303    #[doc = "Reload or reset counter on next prescaler clock"]
304    #[inline(always)]
305    pub fn presc(self) -> &'a mut crate::W<REG> {
306        self.variant(Prescsyncselect::Presc)
307    }
308    #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"]
309    #[inline(always)]
310    pub fn resync(self) -> &'a mut crate::W<REG> {
311        self.variant(Prescsyncselect::Resync)
312    }
313}
314#[doc = "Field `ALOCK` reader - Auto Lock"]
315pub type AlockR = crate::BitReader;
316#[doc = "Field `ALOCK` writer - Auto Lock"]
317pub type AlockW<'a, REG> = crate::BitWriter<'a, REG>;
318#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"]
319pub type Cpten0R = crate::BitReader;
320#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"]
321pub type Cpten0W<'a, REG> = crate::BitWriter<'a, REG>;
322#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"]
323pub type Cpten1R = crate::BitReader;
324#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"]
325pub type Cpten1W<'a, REG> = crate::BitWriter<'a, REG>;
326#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"]
327pub type Cpten2R = crate::BitReader;
328#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"]
329pub type Cpten2W<'a, REG> = crate::BitWriter<'a, REG>;
330#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"]
331pub type Cpten3R = crate::BitReader;
332#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"]
333pub type Cpten3W<'a, REG> = crate::BitWriter<'a, REG>;
334impl R {
335    #[doc = "Bit 0 - Software Reset"]
336    #[inline(always)]
337    pub fn swrst(&self) -> SwrstR {
338        SwrstR::new((self.bits & 1) != 0)
339    }
340    #[doc = "Bit 1 - Enable"]
341    #[inline(always)]
342    pub fn enable(&self) -> EnableR {
343        EnableR::new(((self.bits >> 1) & 1) != 0)
344    }
345    #[doc = "Bits 5:6 - Enhanced Resolution"]
346    #[inline(always)]
347    pub fn resolution(&self) -> ResolutionR {
348        ResolutionR::new(((self.bits >> 5) & 3) as u8)
349    }
350    #[doc = "Bits 8:10 - Prescaler"]
351    #[inline(always)]
352    pub fn prescaler(&self) -> PrescalerR {
353        PrescalerR::new(((self.bits >> 8) & 7) as u8)
354    }
355    #[doc = "Bit 11 - Run in Standby"]
356    #[inline(always)]
357    pub fn runstdby(&self) -> RunstdbyR {
358        RunstdbyR::new(((self.bits >> 11) & 1) != 0)
359    }
360    #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"]
361    #[inline(always)]
362    pub fn prescsync(&self) -> PrescsyncR {
363        PrescsyncR::new(((self.bits >> 12) & 3) as u8)
364    }
365    #[doc = "Bit 14 - Auto Lock"]
366    #[inline(always)]
367    pub fn alock(&self) -> AlockR {
368        AlockR::new(((self.bits >> 14) & 1) != 0)
369    }
370    #[doc = "Bit 24 - Capture Channel 0 Enable"]
371    #[inline(always)]
372    pub fn cpten0(&self) -> Cpten0R {
373        Cpten0R::new(((self.bits >> 24) & 1) != 0)
374    }
375    #[doc = "Bit 25 - Capture Channel 1 Enable"]
376    #[inline(always)]
377    pub fn cpten1(&self) -> Cpten1R {
378        Cpten1R::new(((self.bits >> 25) & 1) != 0)
379    }
380    #[doc = "Bit 26 - Capture Channel 2 Enable"]
381    #[inline(always)]
382    pub fn cpten2(&self) -> Cpten2R {
383        Cpten2R::new(((self.bits >> 26) & 1) != 0)
384    }
385    #[doc = "Bit 27 - Capture Channel 3 Enable"]
386    #[inline(always)]
387    pub fn cpten3(&self) -> Cpten3R {
388        Cpten3R::new(((self.bits >> 27) & 1) != 0)
389    }
390}
391impl W {
392    #[doc = "Bit 0 - Software Reset"]
393    #[inline(always)]
394    #[must_use]
395    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
396        SwrstW::new(self, 0)
397    }
398    #[doc = "Bit 1 - Enable"]
399    #[inline(always)]
400    #[must_use]
401    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
402        EnableW::new(self, 1)
403    }
404    #[doc = "Bits 5:6 - Enhanced Resolution"]
405    #[inline(always)]
406    #[must_use]
407    pub fn resolution(&mut self) -> ResolutionW<CtrlaSpec> {
408        ResolutionW::new(self, 5)
409    }
410    #[doc = "Bits 8:10 - Prescaler"]
411    #[inline(always)]
412    #[must_use]
413    pub fn prescaler(&mut self) -> PrescalerW<CtrlaSpec> {
414        PrescalerW::new(self, 8)
415    }
416    #[doc = "Bit 11 - Run in Standby"]
417    #[inline(always)]
418    #[must_use]
419    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
420        RunstdbyW::new(self, 11)
421    }
422    #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"]
423    #[inline(always)]
424    #[must_use]
425    pub fn prescsync(&mut self) -> PrescsyncW<CtrlaSpec> {
426        PrescsyncW::new(self, 12)
427    }
428    #[doc = "Bit 14 - Auto Lock"]
429    #[inline(always)]
430    #[must_use]
431    pub fn alock(&mut self) -> AlockW<CtrlaSpec> {
432        AlockW::new(self, 14)
433    }
434    #[doc = "Bit 24 - Capture Channel 0 Enable"]
435    #[inline(always)]
436    #[must_use]
437    pub fn cpten0(&mut self) -> Cpten0W<CtrlaSpec> {
438        Cpten0W::new(self, 24)
439    }
440    #[doc = "Bit 25 - Capture Channel 1 Enable"]
441    #[inline(always)]
442    #[must_use]
443    pub fn cpten1(&mut self) -> Cpten1W<CtrlaSpec> {
444        Cpten1W::new(self, 25)
445    }
446    #[doc = "Bit 26 - Capture Channel 2 Enable"]
447    #[inline(always)]
448    #[must_use]
449    pub fn cpten2(&mut self) -> Cpten2W<CtrlaSpec> {
450        Cpten2W::new(self, 26)
451    }
452    #[doc = "Bit 27 - Capture Channel 3 Enable"]
453    #[inline(always)]
454    #[must_use]
455    pub fn cpten3(&mut self) -> Cpten3W<CtrlaSpec> {
456        Cpten3W::new(self, 27)
457    }
458}
459#[doc = "Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
460pub struct CtrlaSpec;
461impl crate::RegisterSpec for CtrlaSpec {
462    type Ux = u32;
463}
464#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
465impl crate::Readable for CtrlaSpec {}
466#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
467impl crate::Writable for CtrlaSpec {
468    type Safety = crate::Unsafe;
469    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
470    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
471}
472#[doc = "`reset()` method sets CTRLA to value 0"]
473impl crate::Resettable for CtrlaSpec {
474    const RESET_VALUE: u32 = 0;
475}
atsamd11d/tcc0/ctrla.rs

atsamd11d/tcc0/
ctrla.rs
