atsamd11d/tc1/count16/
ctrla.rs

Help
1#[doc = "Register `CTRLA` reader"]
2pub type R = crate::R<CtrlaSpec>;
3#[doc = "Register `CTRLA` writer"]
4pub type W = crate::W<CtrlaSpec>;
5#[doc = "Field `SWRST` writer - Software Reset"]
6pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `ENABLE` reader - Enable"]
8pub type EnableR = crate::BitReader;
9#[doc = "Field `ENABLE` writer - Enable"]
10pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "TC Mode\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum Modeselect {
15    #[doc = "0: Counter in 16-bit mode"]
16    Count16 = 0,
17    #[doc = "1: Counter in 8-bit mode"]
18    Count8 = 1,
19    #[doc = "2: Counter in 32-bit mode"]
20    Count32 = 2,
21}
22impl From<Modeselect> for u8 {
23    #[inline(always)]
24    fn from(variant: Modeselect) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for Modeselect {
29    type Ux = u8;
30}
31impl crate::IsEnum for Modeselect {}
32#[doc = "Field `MODE` reader - TC Mode"]
33pub type ModeR = crate::FieldReader<Modeselect>;
34impl ModeR {
35    #[doc = "Get enumerated values variant"]
36    #[inline(always)]
37    pub const fn variant(&self) -> Option<Modeselect> {
38        match self.bits {
39            0 => Some(Modeselect::Count16),
40            1 => Some(Modeselect::Count8),
41            2 => Some(Modeselect::Count32),
42            _ => None,
43        }
44    }
45    #[doc = "Counter in 16-bit mode"]
46    #[inline(always)]
47    pub fn is_count16(&self) -> bool {
48        *self == Modeselect::Count16
49    }
50    #[doc = "Counter in 8-bit mode"]
51    #[inline(always)]
52    pub fn is_count8(&self) -> bool {
53        *self == Modeselect::Count8
54    }
55    #[doc = "Counter in 32-bit mode"]
56    #[inline(always)]
57    pub fn is_count32(&self) -> bool {
58        *self == Modeselect::Count32
59    }
60}
61#[doc = "Field `MODE` writer - TC Mode"]
62pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
63impl<'a, REG> ModeW<'a, REG>
64where
65    REG: crate::Writable + crate::RegisterSpec,
66    REG::Ux: From<u8>,
67{
68    #[doc = "Counter in 16-bit mode"]
69    #[inline(always)]
70    pub fn count16(self) -> &'a mut crate::W<REG> {
71        self.variant(Modeselect::Count16)
72    }
73    #[doc = "Counter in 8-bit mode"]
74    #[inline(always)]
75    pub fn count8(self) -> &'a mut crate::W<REG> {
76        self.variant(Modeselect::Count8)
77    }
78    #[doc = "Counter in 32-bit mode"]
79    #[inline(always)]
80    pub fn count32(self) -> &'a mut crate::W<REG> {
81        self.variant(Modeselect::Count32)
82    }
83}
84#[doc = "Waveform Generation Operation\n\nValue on reset: 0"]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86#[repr(u8)]
87pub enum Wavegenselect {
88    #[doc = "0: `0`"]
89    Nfrq = 0,
90    #[doc = "1: `1`"]
91    Mfrq = 1,
92    #[doc = "2: `10`"]
93    Npwm = 2,
94    #[doc = "3: `11`"]
95    Mpwm = 3,
96}
97impl From<Wavegenselect> for u8 {
98    #[inline(always)]
99    fn from(variant: Wavegenselect) -> Self {
100        variant as _
101    }
102}
103impl crate::FieldSpec for Wavegenselect {
104    type Ux = u8;
105}
106impl crate::IsEnum for Wavegenselect {}
107#[doc = "Field `WAVEGEN` reader - Waveform Generation Operation"]
108pub type WavegenR = crate::FieldReader<Wavegenselect>;
109impl WavegenR {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub const fn variant(&self) -> Wavegenselect {
113        match self.bits {
114            0 => Wavegenselect::Nfrq,
115            1 => Wavegenselect::Mfrq,
116            2 => Wavegenselect::Npwm,
117            3 => Wavegenselect::Mpwm,
118            _ => unreachable!(),
119        }
120    }
121    #[doc = "`0`"]
122    #[inline(always)]
123    pub fn is_nfrq(&self) -> bool {
124        *self == Wavegenselect::Nfrq
125    }
126    #[doc = "`1`"]
127    #[inline(always)]
128    pub fn is_mfrq(&self) -> bool {
129        *self == Wavegenselect::Mfrq
130    }
131    #[doc = "`10`"]
132    #[inline(always)]
133    pub fn is_npwm(&self) -> bool {
134        *self == Wavegenselect::Npwm
135    }
136    #[doc = "`11`"]
137    #[inline(always)]
138    pub fn is_mpwm(&self) -> bool {
139        *self == Wavegenselect::Mpwm
140    }
141}
142#[doc = "Field `WAVEGEN` writer - Waveform Generation Operation"]
143pub type WavegenW<'a, REG> = crate::FieldWriter<'a, REG, 2, Wavegenselect, crate::Safe>;
144impl<'a, REG> WavegenW<'a, REG>
145where
146    REG: crate::Writable + crate::RegisterSpec,
147    REG::Ux: From<u8>,
148{
149    #[doc = "`0`"]
150    #[inline(always)]
151    pub fn nfrq(self) -> &'a mut crate::W<REG> {
152        self.variant(Wavegenselect::Nfrq)
153    }
154    #[doc = "`1`"]
155    #[inline(always)]
156    pub fn mfrq(self) -> &'a mut crate::W<REG> {
157        self.variant(Wavegenselect::Mfrq)
158    }
159    #[doc = "`10`"]
160    #[inline(always)]
161    pub fn npwm(self) -> &'a mut crate::W<REG> {
162        self.variant(Wavegenselect::Npwm)
163    }
164    #[doc = "`11`"]
165    #[inline(always)]
166    pub fn mpwm(self) -> &'a mut crate::W<REG> {
167        self.variant(Wavegenselect::Mpwm)
168    }
169}
170#[doc = "Prescaler\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum Prescalerselect {
174    #[doc = "0: Prescaler: GCLK_TC"]
175    Div1 = 0,
176    #[doc = "1: Prescaler: GCLK_TC/2"]
177    Div2 = 1,
178    #[doc = "2: Prescaler: GCLK_TC/4"]
179    Div4 = 2,
180    #[doc = "3: Prescaler: GCLK_TC/8"]
181    Div8 = 3,
182    #[doc = "4: Prescaler: GCLK_TC/16"]
183    Div16 = 4,
184    #[doc = "5: Prescaler: GCLK_TC/64"]
185    Div64 = 5,
186    #[doc = "6: Prescaler: GCLK_TC/256"]
187    Div256 = 6,
188    #[doc = "7: Prescaler: GCLK_TC/1024"]
189    Div1024 = 7,
190}
191impl From<Prescalerselect> for u8 {
192    #[inline(always)]
193    fn from(variant: Prescalerselect) -> Self {
194        variant as _
195    }
196}
197impl crate::FieldSpec for Prescalerselect {
198    type Ux = u8;
199}
200impl crate::IsEnum for Prescalerselect {}
201#[doc = "Field `PRESCALER` reader - Prescaler"]
202pub type PrescalerR = crate::FieldReader<Prescalerselect>;
203impl PrescalerR {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub const fn variant(&self) -> Prescalerselect {
207        match self.bits {
208            0 => Prescalerselect::Div1,
209            1 => Prescalerselect::Div2,
210            2 => Prescalerselect::Div4,
211            3 => Prescalerselect::Div8,
212            4 => Prescalerselect::Div16,
213            5 => Prescalerselect::Div64,
214            6 => Prescalerselect::Div256,
215            7 => Prescalerselect::Div1024,
216            _ => unreachable!(),
217        }
218    }
219    #[doc = "Prescaler: GCLK_TC"]
220    #[inline(always)]
221    pub fn is_div1(&self) -> bool {
222        *self == Prescalerselect::Div1
223    }
224    #[doc = "Prescaler: GCLK_TC/2"]
225    #[inline(always)]
226    pub fn is_div2(&self) -> bool {
227        *self == Prescalerselect::Div2
228    }
229    #[doc = "Prescaler: GCLK_TC/4"]
230    #[inline(always)]
231    pub fn is_div4(&self) -> bool {
232        *self == Prescalerselect::Div4
233    }
234    #[doc = "Prescaler: GCLK_TC/8"]
235    #[inline(always)]
236    pub fn is_div8(&self) -> bool {
237        *self == Prescalerselect::Div8
238    }
239    #[doc = "Prescaler: GCLK_TC/16"]
240    #[inline(always)]
241    pub fn is_div16(&self) -> bool {
242        *self == Prescalerselect::Div16
243    }
244    #[doc = "Prescaler: GCLK_TC/64"]
245    #[inline(always)]
246    pub fn is_div64(&self) -> bool {
247        *self == Prescalerselect::Div64
248    }
249    #[doc = "Prescaler: GCLK_TC/256"]
250    #[inline(always)]
251    pub fn is_div256(&self) -> bool {
252        *self == Prescalerselect::Div256
253    }
254    #[doc = "Prescaler: GCLK_TC/1024"]
255    #[inline(always)]
256    pub fn is_div1024(&self) -> bool {
257        *self == Prescalerselect::Div1024
258    }
259}
260#[doc = "Field `PRESCALER` writer - Prescaler"]
261pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 3, Prescalerselect, crate::Safe>;
262impl<'a, REG> PrescalerW<'a, REG>
263where
264    REG: crate::Writable + crate::RegisterSpec,
265    REG::Ux: From<u8>,
266{
267    #[doc = "Prescaler: GCLK_TC"]
268    #[inline(always)]
269    pub fn div1(self) -> &'a mut crate::W<REG> {
270        self.variant(Prescalerselect::Div1)
271    }
272    #[doc = "Prescaler: GCLK_TC/2"]
273    #[inline(always)]
274    pub fn div2(self) -> &'a mut crate::W<REG> {
275        self.variant(Prescalerselect::Div2)
276    }
277    #[doc = "Prescaler: GCLK_TC/4"]
278    #[inline(always)]
279    pub fn div4(self) -> &'a mut crate::W<REG> {
280        self.variant(Prescalerselect::Div4)
281    }
282    #[doc = "Prescaler: GCLK_TC/8"]
283    #[inline(always)]
284    pub fn div8(self) -> &'a mut crate::W<REG> {
285        self.variant(Prescalerselect::Div8)
286    }
287    #[doc = "Prescaler: GCLK_TC/16"]
288    #[inline(always)]
289    pub fn div16(self) -> &'a mut crate::W<REG> {
290        self.variant(Prescalerselect::Div16)
291    }
292    #[doc = "Prescaler: GCLK_TC/64"]
293    #[inline(always)]
294    pub fn div64(self) -> &'a mut crate::W<REG> {
295        self.variant(Prescalerselect::Div64)
296    }
297    #[doc = "Prescaler: GCLK_TC/256"]
298    #[inline(always)]
299    pub fn div256(self) -> &'a mut crate::W<REG> {
300        self.variant(Prescalerselect::Div256)
301    }
302    #[doc = "Prescaler: GCLK_TC/1024"]
303    #[inline(always)]
304    pub fn div1024(self) -> &'a mut crate::W<REG> {
305        self.variant(Prescalerselect::Div1024)
306    }
307}
308#[doc = "Field `RUNSTDBY` reader - Run in Standby"]
309pub type RunstdbyR = crate::BitReader;
310#[doc = "Field `RUNSTDBY` writer - Run in Standby"]
311pub type RunstdbyW<'a, REG> = crate::BitWriter<'a, REG>;
312#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"]
313#[derive(Clone, Copy, Debug, PartialEq, Eq)]
314#[repr(u8)]
315pub enum Prescsyncselect {
316    #[doc = "0: Reload or reset the counter on next generic clock"]
317    Gclk = 0,
318    #[doc = "1: Reload or reset the counter on next prescaler clock"]
319    Presc = 1,
320    #[doc = "2: Reload or reset the counter on next generic clock. Reset the prescaler counter"]
321    Resync = 2,
322}
323impl From<Prescsyncselect> for u8 {
324    #[inline(always)]
325    fn from(variant: Prescsyncselect) -> Self {
326        variant as _
327    }
328}
329impl crate::FieldSpec for Prescsyncselect {
330    type Ux = u8;
331}
332impl crate::IsEnum for Prescsyncselect {}
333#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"]
334pub type PrescsyncR = crate::FieldReader<Prescsyncselect>;
335impl PrescsyncR {
336    #[doc = "Get enumerated values variant"]
337    #[inline(always)]
338    pub const fn variant(&self) -> Option<Prescsyncselect> {
339        match self.bits {
340            0 => Some(Prescsyncselect::Gclk),
341            1 => Some(Prescsyncselect::Presc),
342            2 => Some(Prescsyncselect::Resync),
343            _ => None,
344        }
345    }
346    #[doc = "Reload or reset the counter on next generic clock"]
347    #[inline(always)]
348    pub fn is_gclk(&self) -> bool {
349        *self == Prescsyncselect::Gclk
350    }
351    #[doc = "Reload or reset the counter on next prescaler clock"]
352    #[inline(always)]
353    pub fn is_presc(&self) -> bool {
354        *self == Prescsyncselect::Presc
355    }
356    #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"]
357    #[inline(always)]
358    pub fn is_resync(&self) -> bool {
359        *self == Prescsyncselect::Resync
360    }
361}
362#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"]
363pub type PrescsyncW<'a, REG> = crate::FieldWriter<'a, REG, 2, Prescsyncselect>;
364impl<'a, REG> PrescsyncW<'a, REG>
365where
366    REG: crate::Writable + crate::RegisterSpec,
367    REG::Ux: From<u8>,
368{
369    #[doc = "Reload or reset the counter on next generic clock"]
370    #[inline(always)]
371    pub fn gclk(self) -> &'a mut crate::W<REG> {
372        self.variant(Prescsyncselect::Gclk)
373    }
374    #[doc = "Reload or reset the counter on next prescaler clock"]
375    #[inline(always)]
376    pub fn presc(self) -> &'a mut crate::W<REG> {
377        self.variant(Prescsyncselect::Presc)
378    }
379    #[doc = "Reload or reset the counter on next generic clock. Reset the prescaler counter"]
380    #[inline(always)]
381    pub fn resync(self) -> &'a mut crate::W<REG> {
382        self.variant(Prescsyncselect::Resync)
383    }
384}
385impl R {
386    #[doc = "Bit 1 - Enable"]
387    #[inline(always)]
388    pub fn enable(&self) -> EnableR {
389        EnableR::new(((self.bits >> 1) & 1) != 0)
390    }
391    #[doc = "Bits 2:3 - TC Mode"]
392    #[inline(always)]
393    pub fn mode(&self) -> ModeR {
394        ModeR::new(((self.bits >> 2) & 3) as u8)
395    }
396    #[doc = "Bits 5:6 - Waveform Generation Operation"]
397    #[inline(always)]
398    pub fn wavegen(&self) -> WavegenR {
399        WavegenR::new(((self.bits >> 5) & 3) as u8)
400    }
401    #[doc = "Bits 8:10 - Prescaler"]
402    #[inline(always)]
403    pub fn prescaler(&self) -> PrescalerR {
404        PrescalerR::new(((self.bits >> 8) & 7) as u8)
405    }
406    #[doc = "Bit 11 - Run in Standby"]
407    #[inline(always)]
408    pub fn runstdby(&self) -> RunstdbyR {
409        RunstdbyR::new(((self.bits >> 11) & 1) != 0)
410    }
411    #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"]
412    #[inline(always)]
413    pub fn prescsync(&self) -> PrescsyncR {
414        PrescsyncR::new(((self.bits >> 12) & 3) as u8)
415    }
416}
417impl W {
418    #[doc = "Bit 0 - Software Reset"]
419    #[inline(always)]
420    #[must_use]
421    pub fn swrst(&mut self) -> SwrstW<CtrlaSpec> {
422        SwrstW::new(self, 0)
423    }
424    #[doc = "Bit 1 - Enable"]
425    #[inline(always)]
426    #[must_use]
427    pub fn enable(&mut self) -> EnableW<CtrlaSpec> {
428        EnableW::new(self, 1)
429    }
430    #[doc = "Bits 2:3 - TC Mode"]
431    #[inline(always)]
432    #[must_use]
433    pub fn mode(&mut self) -> ModeW<CtrlaSpec> {
434        ModeW::new(self, 2)
435    }
436    #[doc = "Bits 5:6 - Waveform Generation Operation"]
437    #[inline(always)]
438    #[must_use]
439    pub fn wavegen(&mut self) -> WavegenW<CtrlaSpec> {
440        WavegenW::new(self, 5)
441    }
442    #[doc = "Bits 8:10 - Prescaler"]
443    #[inline(always)]
444    #[must_use]
445    pub fn prescaler(&mut self) -> PrescalerW<CtrlaSpec> {
446        PrescalerW::new(self, 8)
447    }
448    #[doc = "Bit 11 - Run in Standby"]
449    #[inline(always)]
450    #[must_use]
451    pub fn runstdby(&mut self) -> RunstdbyW<CtrlaSpec> {
452        RunstdbyW::new(self, 11)
453    }
454    #[doc = "Bits 12:13 - Prescaler and Counter Synchronization"]
455    #[inline(always)]
456    #[must_use]
457    pub fn prescsync(&mut self) -> PrescsyncW<CtrlaSpec> {
458        PrescsyncW::new(self, 12)
459    }
460}
461#[doc = "Control A\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrla::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrla::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
462pub struct CtrlaSpec;
463impl crate::RegisterSpec for CtrlaSpec {
464    type Ux = u16;
465}
466#[doc = "`read()` method returns [`ctrla::R`](R) reader structure"]
467impl crate::Readable for CtrlaSpec {}
468#[doc = "`write(|w| ..)` method takes [`ctrla::W`](W) writer structure"]
469impl crate::Writable for CtrlaSpec {
470    type Safety = crate::Unsafe;
471    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
472    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
473}
474#[doc = "`reset()` method sets CTRLA to value 0"]
475impl crate::Resettable for CtrlaSpec {
476    const RESET_VALUE: u16 = 0;
477}
atsamd11d/tc1/count16/ctrla.rs

atsamd11d/tc1/count16/
ctrla.rs
