atsamd11d/tc1/count8/
ctrlc.rs

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1#[doc = "Register `CTRLC` reader"]
2pub type R = crate::R<CtrlcSpec>;
3#[doc = "Register `CTRLC` writer"]
4pub type W = crate::W<CtrlcSpec>;
5#[doc = "Field `INVEN0` reader - Output Waveform 0 Invert Enable"]
6pub type Inven0R = crate::BitReader;
7#[doc = "Field `INVEN0` writer - Output Waveform 0 Invert Enable"]
8pub type Inven0W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `INVEN1` reader - Output Waveform 1 Invert Enable"]
10pub type Inven1R = crate::BitReader;
11#[doc = "Field `INVEN1` writer - Output Waveform 1 Invert Enable"]
12pub type Inven1W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"]
14pub type Cpten0R = crate::BitReader;
15#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"]
16pub type Cpten0W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"]
18pub type Cpten1R = crate::BitReader;
19#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"]
20pub type Cpten1W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Output Waveform 0 Invert Enable"]
23    #[inline(always)]
24    pub fn inven0(&self) -> Inven0R {
25        Inven0R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Output Waveform 1 Invert Enable"]
28    #[inline(always)]
29    pub fn inven1(&self) -> Inven1R {
30        Inven1R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 4 - Capture Channel 0 Enable"]
33    #[inline(always)]
34    pub fn cpten0(&self) -> Cpten0R {
35        Cpten0R::new(((self.bits >> 4) & 1) != 0)
36    }
37    #[doc = "Bit 5 - Capture Channel 1 Enable"]
38    #[inline(always)]
39    pub fn cpten1(&self) -> Cpten1R {
40        Cpten1R::new(((self.bits >> 5) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Output Waveform 0 Invert Enable"]
45    #[inline(always)]
46    #[must_use]
47    pub fn inven0(&mut self) -> Inven0W<CtrlcSpec> {
48        Inven0W::new(self, 0)
49    }
50    #[doc = "Bit 1 - Output Waveform 1 Invert Enable"]
51    #[inline(always)]
52    #[must_use]
53    pub fn inven1(&mut self) -> Inven1W<CtrlcSpec> {
54        Inven1W::new(self, 1)
55    }
56    #[doc = "Bit 4 - Capture Channel 0 Enable"]
57    #[inline(always)]
58    #[must_use]
59    pub fn cpten0(&mut self) -> Cpten0W<CtrlcSpec> {
60        Cpten0W::new(self, 4)
61    }
62    #[doc = "Bit 5 - Capture Channel 1 Enable"]
63    #[inline(always)]
64    #[must_use]
65    pub fn cpten1(&mut self) -> Cpten1W<CtrlcSpec> {
66        Cpten1W::new(self, 5)
67    }
68}
69#[doc = "Control C\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct CtrlcSpec;
71impl crate::RegisterSpec for CtrlcSpec {
72    type Ux = u8;
73}
74#[doc = "`read()` method returns [`ctrlc::R`](R) reader structure"]
75impl crate::Readable for CtrlcSpec {}
76#[doc = "`write(|w| ..)` method takes [`ctrlc::W`](W) writer structure"]
77impl crate::Writable for CtrlcSpec {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
81}
82#[doc = "`reset()` method sets CTRLC to value 0"]
83impl crate::Resettable for CtrlcSpec {
84    const RESET_VALUE: u8 = 0;
85}
atsamd11d/tc1/count8/ctrlc.rs

atsamd11d/tc1/count8/
ctrlc.rs
