atsamd11d/sysctrl/
dpllctrlb.rs

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1#[doc = "Register `DPLLCTRLB` reader"]
2pub type R = crate::R<DpllctrlbSpec>;
3#[doc = "Register `DPLLCTRLB` writer"]
4pub type W = crate::W<DpllctrlbSpec>;
5#[doc = "Proportional Integral Filter Selection\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Filterselect {
9    #[doc = "0: Default filter mode"]
10    Default = 0,
11    #[doc = "1: Low bandwidth filter"]
12    Lbfilt = 1,
13    #[doc = "2: High bandwidth filter"]
14    Hbfilt = 2,
15    #[doc = "3: High damping filter"]
16    Hdfilt = 3,
17}
18impl From<Filterselect> for u8 {
19    #[inline(always)]
20    fn from(variant: Filterselect) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for Filterselect {
25    type Ux = u8;
26}
27impl crate::IsEnum for Filterselect {}
28#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"]
29pub type FilterR = crate::FieldReader<Filterselect>;
30impl FilterR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Filterselect {
34        match self.bits {
35            0 => Filterselect::Default,
36            1 => Filterselect::Lbfilt,
37            2 => Filterselect::Hbfilt,
38            3 => Filterselect::Hdfilt,
39            _ => unreachable!(),
40        }
41    }
42    #[doc = "Default filter mode"]
43    #[inline(always)]
44    pub fn is_default(&self) -> bool {
45        *self == Filterselect::Default
46    }
47    #[doc = "Low bandwidth filter"]
48    #[inline(always)]
49    pub fn is_lbfilt(&self) -> bool {
50        *self == Filterselect::Lbfilt
51    }
52    #[doc = "High bandwidth filter"]
53    #[inline(always)]
54    pub fn is_hbfilt(&self) -> bool {
55        *self == Filterselect::Hbfilt
56    }
57    #[doc = "High damping filter"]
58    #[inline(always)]
59    pub fn is_hdfilt(&self) -> bool {
60        *self == Filterselect::Hdfilt
61    }
62}
63#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"]
64pub type FilterW<'a, REG> = crate::FieldWriter<'a, REG, 2, Filterselect, crate::Safe>;
65impl<'a, REG> FilterW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Default filter mode"]
71    #[inline(always)]
72    pub fn default(self) -> &'a mut crate::W<REG> {
73        self.variant(Filterselect::Default)
74    }
75    #[doc = "Low bandwidth filter"]
76    #[inline(always)]
77    pub fn lbfilt(self) -> &'a mut crate::W<REG> {
78        self.variant(Filterselect::Lbfilt)
79    }
80    #[doc = "High bandwidth filter"]
81    #[inline(always)]
82    pub fn hbfilt(self) -> &'a mut crate::W<REG> {
83        self.variant(Filterselect::Hbfilt)
84    }
85    #[doc = "High damping filter"]
86    #[inline(always)]
87    pub fn hdfilt(self) -> &'a mut crate::W<REG> {
88        self.variant(Filterselect::Hdfilt)
89    }
90}
91#[doc = "Field `LPEN` reader - Low-Power Enable"]
92pub type LpenR = crate::BitReader;
93#[doc = "Field `LPEN` writer - Low-Power Enable"]
94pub type LpenW<'a, REG> = crate::BitWriter<'a, REG>;
95#[doc = "Field `WUF` reader - Wake Up Fast"]
96pub type WufR = crate::BitReader;
97#[doc = "Field `WUF` writer - Wake Up Fast"]
98pub type WufW<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Reference Clock Selection\n\nValue on reset: 0"]
100#[derive(Clone, Copy, Debug, PartialEq, Eq)]
101#[repr(u8)]
102pub enum Refclkselect {
103    #[doc = "0: CLK_DPLL_REF0 clock reference"]
104    Ref0 = 0,
105    #[doc = "1: CLK_DPLL_REF1 clock reference"]
106    Ref1 = 1,
107    #[doc = "2: GCLK_DPLL clock reference"]
108    Gclk = 2,
109}
110impl From<Refclkselect> for u8 {
111    #[inline(always)]
112    fn from(variant: Refclkselect) -> Self {
113        variant as _
114    }
115}
116impl crate::FieldSpec for Refclkselect {
117    type Ux = u8;
118}
119impl crate::IsEnum for Refclkselect {}
120#[doc = "Field `REFCLK` reader - Reference Clock Selection"]
121pub type RefclkR = crate::FieldReader<Refclkselect>;
122impl RefclkR {
123    #[doc = "Get enumerated values variant"]
124    #[inline(always)]
125    pub const fn variant(&self) -> Option<Refclkselect> {
126        match self.bits {
127            0 => Some(Refclkselect::Ref0),
128            1 => Some(Refclkselect::Ref1),
129            2 => Some(Refclkselect::Gclk),
130            _ => None,
131        }
132    }
133    #[doc = "CLK_DPLL_REF0 clock reference"]
134    #[inline(always)]
135    pub fn is_ref0(&self) -> bool {
136        *self == Refclkselect::Ref0
137    }
138    #[doc = "CLK_DPLL_REF1 clock reference"]
139    #[inline(always)]
140    pub fn is_ref1(&self) -> bool {
141        *self == Refclkselect::Ref1
142    }
143    #[doc = "GCLK_DPLL clock reference"]
144    #[inline(always)]
145    pub fn is_gclk(&self) -> bool {
146        *self == Refclkselect::Gclk
147    }
148}
149#[doc = "Field `REFCLK` writer - Reference Clock Selection"]
150pub type RefclkW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refclkselect>;
151impl<'a, REG> RefclkW<'a, REG>
152where
153    REG: crate::Writable + crate::RegisterSpec,
154    REG::Ux: From<u8>,
155{
156    #[doc = "CLK_DPLL_REF0 clock reference"]
157    #[inline(always)]
158    pub fn ref0(self) -> &'a mut crate::W<REG> {
159        self.variant(Refclkselect::Ref0)
160    }
161    #[doc = "CLK_DPLL_REF1 clock reference"]
162    #[inline(always)]
163    pub fn ref1(self) -> &'a mut crate::W<REG> {
164        self.variant(Refclkselect::Ref1)
165    }
166    #[doc = "GCLK_DPLL clock reference"]
167    #[inline(always)]
168    pub fn gclk(self) -> &'a mut crate::W<REG> {
169        self.variant(Refclkselect::Gclk)
170    }
171}
172#[doc = "Lock Time\n\nValue on reset: 0"]
173#[derive(Clone, Copy, Debug, PartialEq, Eq)]
174#[repr(u8)]
175pub enum Ltimeselect {
176    #[doc = "0: Default No time-out"]
177    None = 0,
178    #[doc = "4: 8MS Time-out if no lock within 8 ms"]
179    _8ms = 4,
180    #[doc = "5: 9MS Time-out if no lock within 9 ms"]
181    _9ms = 5,
182    #[doc = "6: 10MS Time-out if no lock within 10 ms"]
183    _10ms = 6,
184    #[doc = "7: 11MS Time-out if no lock within 11 ms"]
185    _11ms = 7,
186}
187impl From<Ltimeselect> for u8 {
188    #[inline(always)]
189    fn from(variant: Ltimeselect) -> Self {
190        variant as _
191    }
192}
193impl crate::FieldSpec for Ltimeselect {
194    type Ux = u8;
195}
196impl crate::IsEnum for Ltimeselect {}
197#[doc = "Field `LTIME` reader - Lock Time"]
198pub type LtimeR = crate::FieldReader<Ltimeselect>;
199impl LtimeR {
200    #[doc = "Get enumerated values variant"]
201    #[inline(always)]
202    pub const fn variant(&self) -> Option<Ltimeselect> {
203        match self.bits {
204            0 => Some(Ltimeselect::None),
205            4 => Some(Ltimeselect::_8ms),
206            5 => Some(Ltimeselect::_9ms),
207            6 => Some(Ltimeselect::_10ms),
208            7 => Some(Ltimeselect::_11ms),
209            _ => None,
210        }
211    }
212    #[doc = "Default No time-out"]
213    #[inline(always)]
214    pub fn is_none(&self) -> bool {
215        *self == Ltimeselect::None
216    }
217    #[doc = "8MS Time-out if no lock within 8 ms"]
218    #[inline(always)]
219    pub fn is_8ms(&self) -> bool {
220        *self == Ltimeselect::_8ms
221    }
222    #[doc = "9MS Time-out if no lock within 9 ms"]
223    #[inline(always)]
224    pub fn is_9ms(&self) -> bool {
225        *self == Ltimeselect::_9ms
226    }
227    #[doc = "10MS Time-out if no lock within 10 ms"]
228    #[inline(always)]
229    pub fn is_10ms(&self) -> bool {
230        *self == Ltimeselect::_10ms
231    }
232    #[doc = "11MS Time-out if no lock within 11 ms"]
233    #[inline(always)]
234    pub fn is_11ms(&self) -> bool {
235        *self == Ltimeselect::_11ms
236    }
237}
238#[doc = "Field `LTIME` writer - Lock Time"]
239pub type LtimeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ltimeselect>;
240impl<'a, REG> LtimeW<'a, REG>
241where
242    REG: crate::Writable + crate::RegisterSpec,
243    REG::Ux: From<u8>,
244{
245    #[doc = "Default No time-out"]
246    #[inline(always)]
247    pub fn none(self) -> &'a mut crate::W<REG> {
248        self.variant(Ltimeselect::None)
249    }
250    #[doc = "8MS Time-out if no lock within 8 ms"]
251    #[inline(always)]
252    pub fn _8ms(self) -> &'a mut crate::W<REG> {
253        self.variant(Ltimeselect::_8ms)
254    }
255    #[doc = "9MS Time-out if no lock within 9 ms"]
256    #[inline(always)]
257    pub fn _9ms(self) -> &'a mut crate::W<REG> {
258        self.variant(Ltimeselect::_9ms)
259    }
260    #[doc = "10MS Time-out if no lock within 10 ms"]
261    #[inline(always)]
262    pub fn _10ms(self) -> &'a mut crate::W<REG> {
263        self.variant(Ltimeselect::_10ms)
264    }
265    #[doc = "11MS Time-out if no lock within 11 ms"]
266    #[inline(always)]
267    pub fn _11ms(self) -> &'a mut crate::W<REG> {
268        self.variant(Ltimeselect::_11ms)
269    }
270}
271#[doc = "Field `LBYPASS` reader - Lock Bypass"]
272pub type LbypassR = crate::BitReader;
273#[doc = "Field `LBYPASS` writer - Lock Bypass"]
274pub type LbypassW<'a, REG> = crate::BitWriter<'a, REG>;
275#[doc = "Field `DIV` reader - Clock Divider"]
276pub type DivR = crate::FieldReader<u16>;
277#[doc = "Field `DIV` writer - Clock Divider"]
278pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
279impl R {
280    #[doc = "Bits 0:1 - Proportional Integral Filter Selection"]
281    #[inline(always)]
282    pub fn filter(&self) -> FilterR {
283        FilterR::new((self.bits & 3) as u8)
284    }
285    #[doc = "Bit 2 - Low-Power Enable"]
286    #[inline(always)]
287    pub fn lpen(&self) -> LpenR {
288        LpenR::new(((self.bits >> 2) & 1) != 0)
289    }
290    #[doc = "Bit 3 - Wake Up Fast"]
291    #[inline(always)]
292    pub fn wuf(&self) -> WufR {
293        WufR::new(((self.bits >> 3) & 1) != 0)
294    }
295    #[doc = "Bits 4:5 - Reference Clock Selection"]
296    #[inline(always)]
297    pub fn refclk(&self) -> RefclkR {
298        RefclkR::new(((self.bits >> 4) & 3) as u8)
299    }
300    #[doc = "Bits 8:10 - Lock Time"]
301    #[inline(always)]
302    pub fn ltime(&self) -> LtimeR {
303        LtimeR::new(((self.bits >> 8) & 7) as u8)
304    }
305    #[doc = "Bit 12 - Lock Bypass"]
306    #[inline(always)]
307    pub fn lbypass(&self) -> LbypassR {
308        LbypassR::new(((self.bits >> 12) & 1) != 0)
309    }
310    #[doc = "Bits 16:26 - Clock Divider"]
311    #[inline(always)]
312    pub fn div(&self) -> DivR {
313        DivR::new(((self.bits >> 16) & 0x07ff) as u16)
314    }
315}
316impl W {
317    #[doc = "Bits 0:1 - Proportional Integral Filter Selection"]
318    #[inline(always)]
319    #[must_use]
320    pub fn filter(&mut self) -> FilterW<DpllctrlbSpec> {
321        FilterW::new(self, 0)
322    }
323    #[doc = "Bit 2 - Low-Power Enable"]
324    #[inline(always)]
325    #[must_use]
326    pub fn lpen(&mut self) -> LpenW<DpllctrlbSpec> {
327        LpenW::new(self, 2)
328    }
329    #[doc = "Bit 3 - Wake Up Fast"]
330    #[inline(always)]
331    #[must_use]
332    pub fn wuf(&mut self) -> WufW<DpllctrlbSpec> {
333        WufW::new(self, 3)
334    }
335    #[doc = "Bits 4:5 - Reference Clock Selection"]
336    #[inline(always)]
337    #[must_use]
338    pub fn refclk(&mut self) -> RefclkW<DpllctrlbSpec> {
339        RefclkW::new(self, 4)
340    }
341    #[doc = "Bits 8:10 - Lock Time"]
342    #[inline(always)]
343    #[must_use]
344    pub fn ltime(&mut self) -> LtimeW<DpllctrlbSpec> {
345        LtimeW::new(self, 8)
346    }
347    #[doc = "Bit 12 - Lock Bypass"]
348    #[inline(always)]
349    #[must_use]
350    pub fn lbypass(&mut self) -> LbypassW<DpllctrlbSpec> {
351        LbypassW::new(self, 12)
352    }
353    #[doc = "Bits 16:26 - Clock Divider"]
354    #[inline(always)]
355    #[must_use]
356    pub fn div(&mut self) -> DivW<DpllctrlbSpec> {
357        DivW::new(self, 16)
358    }
359}
360#[doc = "DPLL Control B\n\nYou can [`read`](crate::Reg::read) this register and get [`dpllctrlb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpllctrlb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
361pub struct DpllctrlbSpec;
362impl crate::RegisterSpec for DpllctrlbSpec {
363    type Ux = u32;
364}
365#[doc = "`read()` method returns [`dpllctrlb::R`](R) reader structure"]
366impl crate::Readable for DpllctrlbSpec {}
367#[doc = "`write(|w| ..)` method takes [`dpllctrlb::W`](W) writer structure"]
368impl crate::Writable for DpllctrlbSpec {
369    type Safety = crate::Unsafe;
370    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
371    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
372}
373#[doc = "`reset()` method sets DPLLCTRLB to value 0"]
374impl crate::Resettable for DpllctrlbSpec {
375    const RESET_VALUE: u32 = 0;
376}
atsamd11d/sysctrl/dpllctrlb.rs

atsamd11d/sysctrl/
dpllctrlb.rs
