atsamd11d/rtc/mode0/
ctrl.rs

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1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `SWRST` reader - Software Reset"]
6pub type SwrstR = crate::BitReader;
7#[doc = "Field `SWRST` writer - Software Reset"]
8pub type SwrstW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ENABLE` reader - Enable"]
10pub type EnableR = crate::BitReader;
11#[doc = "Field `ENABLE` writer - Enable"]
12pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Operating Mode\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq, Eq)]
15#[repr(u8)]
16pub enum Modeselect {
17    #[doc = "0: Mode 0: 32-bit Counter"]
18    Count32 = 0,
19    #[doc = "1: Mode 1: 16-bit Counter"]
20    Count16 = 1,
21    #[doc = "2: Mode 2: Clock/Calendar"]
22    Clock = 2,
23}
24impl From<Modeselect> for u8 {
25    #[inline(always)]
26    fn from(variant: Modeselect) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Modeselect {
31    type Ux = u8;
32}
33impl crate::IsEnum for Modeselect {}
34#[doc = "Field `MODE` reader - Operating Mode"]
35pub type ModeR = crate::FieldReader<Modeselect>;
36impl ModeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Modeselect> {
40        match self.bits {
41            0 => Some(Modeselect::Count32),
42            1 => Some(Modeselect::Count16),
43            2 => Some(Modeselect::Clock),
44            _ => None,
45        }
46    }
47    #[doc = "Mode 0: 32-bit Counter"]
48    #[inline(always)]
49    pub fn is_count32(&self) -> bool {
50        *self == Modeselect::Count32
51    }
52    #[doc = "Mode 1: 16-bit Counter"]
53    #[inline(always)]
54    pub fn is_count16(&self) -> bool {
55        *self == Modeselect::Count16
56    }
57    #[doc = "Mode 2: Clock/Calendar"]
58    #[inline(always)]
59    pub fn is_clock(&self) -> bool {
60        *self == Modeselect::Clock
61    }
62}
63#[doc = "Field `MODE` writer - Operating Mode"]
64pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Modeselect>;
65impl<'a, REG> ModeW<'a, REG>
66where
67    REG: crate::Writable + crate::RegisterSpec,
68    REG::Ux: From<u8>,
69{
70    #[doc = "Mode 0: 32-bit Counter"]
71    #[inline(always)]
72    pub fn count32(self) -> &'a mut crate::W<REG> {
73        self.variant(Modeselect::Count32)
74    }
75    #[doc = "Mode 1: 16-bit Counter"]
76    #[inline(always)]
77    pub fn count16(self) -> &'a mut crate::W<REG> {
78        self.variant(Modeselect::Count16)
79    }
80    #[doc = "Mode 2: Clock/Calendar"]
81    #[inline(always)]
82    pub fn clock(self) -> &'a mut crate::W<REG> {
83        self.variant(Modeselect::Clock)
84    }
85}
86#[doc = "Field `MATCHCLR` reader - Clear on Match"]
87pub type MatchclrR = crate::BitReader;
88#[doc = "Field `MATCHCLR` writer - Clear on Match"]
89pub type MatchclrW<'a, REG> = crate::BitWriter<'a, REG>;
90#[doc = "Prescaler\n\nValue on reset: 0"]
91#[derive(Clone, Copy, Debug, PartialEq, Eq)]
92#[repr(u8)]
93pub enum Prescalerselect {
94    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
95    Div1 = 0,
96    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/2"]
97    Div2 = 1,
98    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/4"]
99    Div4 = 2,
100    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/8"]
101    Div8 = 3,
102    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/16"]
103    Div16 = 4,
104    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/32"]
105    Div32 = 5,
106    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/64"]
107    Div64 = 6,
108    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/128"]
109    Div128 = 7,
110    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/256"]
111    Div256 = 8,
112    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/512"]
113    Div512 = 9,
114    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/1024"]
115    Div1024 = 10,
116}
117impl From<Prescalerselect> for u8 {
118    #[inline(always)]
119    fn from(variant: Prescalerselect) -> Self {
120        variant as _
121    }
122}
123impl crate::FieldSpec for Prescalerselect {
124    type Ux = u8;
125}
126impl crate::IsEnum for Prescalerselect {}
127#[doc = "Field `PRESCALER` reader - Prescaler"]
128pub type PrescalerR = crate::FieldReader<Prescalerselect>;
129impl PrescalerR {
130    #[doc = "Get enumerated values variant"]
131    #[inline(always)]
132    pub const fn variant(&self) -> Option<Prescalerselect> {
133        match self.bits {
134            0 => Some(Prescalerselect::Div1),
135            1 => Some(Prescalerselect::Div2),
136            2 => Some(Prescalerselect::Div4),
137            3 => Some(Prescalerselect::Div8),
138            4 => Some(Prescalerselect::Div16),
139            5 => Some(Prescalerselect::Div32),
140            6 => Some(Prescalerselect::Div64),
141            7 => Some(Prescalerselect::Div128),
142            8 => Some(Prescalerselect::Div256),
143            9 => Some(Prescalerselect::Div512),
144            10 => Some(Prescalerselect::Div1024),
145            _ => None,
146        }
147    }
148    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
149    #[inline(always)]
150    pub fn is_div1(&self) -> bool {
151        *self == Prescalerselect::Div1
152    }
153    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
154    #[inline(always)]
155    pub fn is_div2(&self) -> bool {
156        *self == Prescalerselect::Div2
157    }
158    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
159    #[inline(always)]
160    pub fn is_div4(&self) -> bool {
161        *self == Prescalerselect::Div4
162    }
163    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
164    #[inline(always)]
165    pub fn is_div8(&self) -> bool {
166        *self == Prescalerselect::Div8
167    }
168    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
169    #[inline(always)]
170    pub fn is_div16(&self) -> bool {
171        *self == Prescalerselect::Div16
172    }
173    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
174    #[inline(always)]
175    pub fn is_div32(&self) -> bool {
176        *self == Prescalerselect::Div32
177    }
178    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
179    #[inline(always)]
180    pub fn is_div64(&self) -> bool {
181        *self == Prescalerselect::Div64
182    }
183    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
184    #[inline(always)]
185    pub fn is_div128(&self) -> bool {
186        *self == Prescalerselect::Div128
187    }
188    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
189    #[inline(always)]
190    pub fn is_div256(&self) -> bool {
191        *self == Prescalerselect::Div256
192    }
193    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
194    #[inline(always)]
195    pub fn is_div512(&self) -> bool {
196        *self == Prescalerselect::Div512
197    }
198    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
199    #[inline(always)]
200    pub fn is_div1024(&self) -> bool {
201        *self == Prescalerselect::Div1024
202    }
203}
204#[doc = "Field `PRESCALER` writer - Prescaler"]
205pub type PrescalerW<'a, REG> = crate::FieldWriter<'a, REG, 4, Prescalerselect>;
206impl<'a, REG> PrescalerW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209    REG::Ux: From<u8>,
210{
211    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
212    #[inline(always)]
213    pub fn div1(self) -> &'a mut crate::W<REG> {
214        self.variant(Prescalerselect::Div1)
215    }
216    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
217    #[inline(always)]
218    pub fn div2(self) -> &'a mut crate::W<REG> {
219        self.variant(Prescalerselect::Div2)
220    }
221    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
222    #[inline(always)]
223    pub fn div4(self) -> &'a mut crate::W<REG> {
224        self.variant(Prescalerselect::Div4)
225    }
226    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
227    #[inline(always)]
228    pub fn div8(self) -> &'a mut crate::W<REG> {
229        self.variant(Prescalerselect::Div8)
230    }
231    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
232    #[inline(always)]
233    pub fn div16(self) -> &'a mut crate::W<REG> {
234        self.variant(Prescalerselect::Div16)
235    }
236    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
237    #[inline(always)]
238    pub fn div32(self) -> &'a mut crate::W<REG> {
239        self.variant(Prescalerselect::Div32)
240    }
241    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
242    #[inline(always)]
243    pub fn div64(self) -> &'a mut crate::W<REG> {
244        self.variant(Prescalerselect::Div64)
245    }
246    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
247    #[inline(always)]
248    pub fn div128(self) -> &'a mut crate::W<REG> {
249        self.variant(Prescalerselect::Div128)
250    }
251    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
252    #[inline(always)]
253    pub fn div256(self) -> &'a mut crate::W<REG> {
254        self.variant(Prescalerselect::Div256)
255    }
256    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
257    #[inline(always)]
258    pub fn div512(self) -> &'a mut crate::W<REG> {
259        self.variant(Prescalerselect::Div512)
260    }
261    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
262    #[inline(always)]
263    pub fn div1024(self) -> &'a mut crate::W<REG> {
264        self.variant(Prescalerselect::Div1024)
265    }
266}
267impl R {
268    #[doc = "Bit 0 - Software Reset"]
269    #[inline(always)]
270    pub fn swrst(&self) -> SwrstR {
271        SwrstR::new((self.bits & 1) != 0)
272    }
273    #[doc = "Bit 1 - Enable"]
274    #[inline(always)]
275    pub fn enable(&self) -> EnableR {
276        EnableR::new(((self.bits >> 1) & 1) != 0)
277    }
278    #[doc = "Bits 2:3 - Operating Mode"]
279    #[inline(always)]
280    pub fn mode(&self) -> ModeR {
281        ModeR::new(((self.bits >> 2) & 3) as u8)
282    }
283    #[doc = "Bit 7 - Clear on Match"]
284    #[inline(always)]
285    pub fn matchclr(&self) -> MatchclrR {
286        MatchclrR::new(((self.bits >> 7) & 1) != 0)
287    }
288    #[doc = "Bits 8:11 - Prescaler"]
289    #[inline(always)]
290    pub fn prescaler(&self) -> PrescalerR {
291        PrescalerR::new(((self.bits >> 8) & 0x0f) as u8)
292    }
293}
294impl W {
295    #[doc = "Bit 0 - Software Reset"]
296    #[inline(always)]
297    #[must_use]
298    pub fn swrst(&mut self) -> SwrstW<CtrlSpec> {
299        SwrstW::new(self, 0)
300    }
301    #[doc = "Bit 1 - Enable"]
302    #[inline(always)]
303    #[must_use]
304    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
305        EnableW::new(self, 1)
306    }
307    #[doc = "Bits 2:3 - Operating Mode"]
308    #[inline(always)]
309    #[must_use]
310    pub fn mode(&mut self) -> ModeW<CtrlSpec> {
311        ModeW::new(self, 2)
312    }
313    #[doc = "Bit 7 - Clear on Match"]
314    #[inline(always)]
315    #[must_use]
316    pub fn matchclr(&mut self) -> MatchclrW<CtrlSpec> {
317        MatchclrW::new(self, 7)
318    }
319    #[doc = "Bits 8:11 - Prescaler"]
320    #[inline(always)]
321    #[must_use]
322    pub fn prescaler(&mut self) -> PrescalerW<CtrlSpec> {
323        PrescalerW::new(self, 8)
324    }
325}
326#[doc = "MODE0 Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
327pub struct CtrlSpec;
328impl crate::RegisterSpec for CtrlSpec {
329    type Ux = u16;
330}
331#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
332impl crate::Readable for CtrlSpec {}
333#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
334impl crate::Writable for CtrlSpec {
335    type Safety = crate::Unsafe;
336    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
337    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
338}
339#[doc = "`reset()` method sets CTRL to value 0"]
340impl crate::Resettable for CtrlSpec {
341    const RESET_VALUE: u16 = 0;
342}
atsamd11d/rtc/mode0/ctrl.rs

atsamd11d/rtc/mode0/
ctrl.rs
