atsamd11d/sysctrl/
intenset.rs

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1#[doc = "Register `INTENSET` reader"]
2pub type R = crate::R<IntensetSpec>;
3#[doc = "Register `INTENSET` writer"]
4pub type W = crate::W<IntensetSpec>;
5#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"]
6pub type XoscrdyR = crate::BitReader;
7#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"]
8pub type XoscrdyW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"]
10pub type Xosc32krdyR = crate::BitReader;
11#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"]
12pub type Xosc32krdyW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OSC32KRDY` reader - OSC32K Ready Interrupt Enable"]
14pub type Osc32krdyR = crate::BitReader;
15#[doc = "Field `OSC32KRDY` writer - OSC32K Ready Interrupt Enable"]
16pub type Osc32krdyW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OSC8MRDY` reader - OSC8M Ready Interrupt Enable"]
18pub type Osc8mrdyR = crate::BitReader;
19#[doc = "Field `OSC8MRDY` writer - OSC8M Ready Interrupt Enable"]
20pub type Osc8mrdyW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"]
22pub type DfllrdyR = crate::BitReader;
23#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"]
24pub type DfllrdyW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"]
26pub type DflloobR = crate::BitReader;
27#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"]
28pub type DflloobW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"]
30pub type DflllckfR = crate::BitReader;
31#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"]
32pub type DflllckfW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"]
34pub type DflllckcR = crate::BitReader;
35#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"]
36pub type DflllckcW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"]
38pub type DfllrcsR = crate::BitReader;
39#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"]
40pub type DfllrcsW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `BOD33RDY` reader - BOD33 Ready Interrupt Enable"]
42pub type Bod33rdyR = crate::BitReader;
43#[doc = "Field `BOD33RDY` writer - BOD33 Ready Interrupt Enable"]
44pub type Bod33rdyW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `BOD33DET` reader - BOD33 Detection Interrupt Enable"]
46pub type Bod33detR = crate::BitReader;
47#[doc = "Field `BOD33DET` writer - BOD33 Detection Interrupt Enable"]
48pub type Bod33detW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready Interrupt Enable"]
50pub type B33srdyR = crate::BitReader;
51#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready Interrupt Enable"]
52pub type B33srdyW<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"]
54pub type DplllckrR = crate::BitReader;
55#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"]
56pub type DplllckrW<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"]
58pub type DplllckfR = crate::BitReader;
59#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"]
60pub type DplllckfW<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `DPLLLTO` reader - DPLL Lock Timeout Interrupt Enable"]
62pub type DpllltoR = crate::BitReader;
63#[doc = "Field `DPLLLTO` writer - DPLL Lock Timeout Interrupt Enable"]
64pub type DpllltoW<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66    #[doc = "Bit 0 - XOSC Ready Interrupt Enable"]
67    #[inline(always)]
68    pub fn xoscrdy(&self) -> XoscrdyR {
69        XoscrdyR::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"]
72    #[inline(always)]
73    pub fn xosc32krdy(&self) -> Xosc32krdyR {
74        Xosc32krdyR::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"]
77    #[inline(always)]
78    pub fn osc32krdy(&self) -> Osc32krdyR {
79        Osc32krdyR::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"]
82    #[inline(always)]
83    pub fn osc8mrdy(&self) -> Osc8mrdyR {
84        Osc8mrdyR::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - DFLL Ready Interrupt Enable"]
87    #[inline(always)]
88    pub fn dfllrdy(&self) -> DfllrdyR {
89        DfllrdyR::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"]
92    #[inline(always)]
93    pub fn dflloob(&self) -> DflloobR {
94        DflloobR::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"]
97    #[inline(always)]
98    pub fn dflllckf(&self) -> DflllckfR {
99        DflllckfR::new(((self.bits >> 6) & 1) != 0)
100    }
101    #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"]
102    #[inline(always)]
103    pub fn dflllckc(&self) -> DflllckcR {
104        DflllckcR::new(((self.bits >> 7) & 1) != 0)
105    }
106    #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"]
107    #[inline(always)]
108    pub fn dfllrcs(&self) -> DfllrcsR {
109        DfllrcsR::new(((self.bits >> 8) & 1) != 0)
110    }
111    #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"]
112    #[inline(always)]
113    pub fn bod33rdy(&self) -> Bod33rdyR {
114        Bod33rdyR::new(((self.bits >> 9) & 1) != 0)
115    }
116    #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"]
117    #[inline(always)]
118    pub fn bod33det(&self) -> Bod33detR {
119        Bod33detR::new(((self.bits >> 10) & 1) != 0)
120    }
121    #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"]
122    #[inline(always)]
123    pub fn b33srdy(&self) -> B33srdyR {
124        B33srdyR::new(((self.bits >> 11) & 1) != 0)
125    }
126    #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"]
127    #[inline(always)]
128    pub fn dplllckr(&self) -> DplllckrR {
129        DplllckrR::new(((self.bits >> 15) & 1) != 0)
130    }
131    #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"]
132    #[inline(always)]
133    pub fn dplllckf(&self) -> DplllckfR {
134        DplllckfR::new(((self.bits >> 16) & 1) != 0)
135    }
136    #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"]
137    #[inline(always)]
138    pub fn dplllto(&self) -> DpllltoR {
139        DpllltoR::new(((self.bits >> 17) & 1) != 0)
140    }
141}
142impl W {
143    #[doc = "Bit 0 - XOSC Ready Interrupt Enable"]
144    #[inline(always)]
145    #[must_use]
146    pub fn xoscrdy(&mut self) -> XoscrdyW<IntensetSpec> {
147        XoscrdyW::new(self, 0)
148    }
149    #[doc = "Bit 1 - XOSC32K Ready Interrupt Enable"]
150    #[inline(always)]
151    #[must_use]
152    pub fn xosc32krdy(&mut self) -> Xosc32krdyW<IntensetSpec> {
153        Xosc32krdyW::new(self, 1)
154    }
155    #[doc = "Bit 2 - OSC32K Ready Interrupt Enable"]
156    #[inline(always)]
157    #[must_use]
158    pub fn osc32krdy(&mut self) -> Osc32krdyW<IntensetSpec> {
159        Osc32krdyW::new(self, 2)
160    }
161    #[doc = "Bit 3 - OSC8M Ready Interrupt Enable"]
162    #[inline(always)]
163    #[must_use]
164    pub fn osc8mrdy(&mut self) -> Osc8mrdyW<IntensetSpec> {
165        Osc8mrdyW::new(self, 3)
166    }
167    #[doc = "Bit 4 - DFLL Ready Interrupt Enable"]
168    #[inline(always)]
169    #[must_use]
170    pub fn dfllrdy(&mut self) -> DfllrdyW<IntensetSpec> {
171        DfllrdyW::new(self, 4)
172    }
173    #[doc = "Bit 5 - DFLL Out Of Bounds Interrupt Enable"]
174    #[inline(always)]
175    #[must_use]
176    pub fn dflloob(&mut self) -> DflloobW<IntensetSpec> {
177        DflloobW::new(self, 5)
178    }
179    #[doc = "Bit 6 - DFLL Lock Fine Interrupt Enable"]
180    #[inline(always)]
181    #[must_use]
182    pub fn dflllckf(&mut self) -> DflllckfW<IntensetSpec> {
183        DflllckfW::new(self, 6)
184    }
185    #[doc = "Bit 7 - DFLL Lock Coarse Interrupt Enable"]
186    #[inline(always)]
187    #[must_use]
188    pub fn dflllckc(&mut self) -> DflllckcW<IntensetSpec> {
189        DflllckcW::new(self, 7)
190    }
191    #[doc = "Bit 8 - DFLL Reference Clock Stopped Interrupt Enable"]
192    #[inline(always)]
193    #[must_use]
194    pub fn dfllrcs(&mut self) -> DfllrcsW<IntensetSpec> {
195        DfllrcsW::new(self, 8)
196    }
197    #[doc = "Bit 9 - BOD33 Ready Interrupt Enable"]
198    #[inline(always)]
199    #[must_use]
200    pub fn bod33rdy(&mut self) -> Bod33rdyW<IntensetSpec> {
201        Bod33rdyW::new(self, 9)
202    }
203    #[doc = "Bit 10 - BOD33 Detection Interrupt Enable"]
204    #[inline(always)]
205    #[must_use]
206    pub fn bod33det(&mut self) -> Bod33detW<IntensetSpec> {
207        Bod33detW::new(self, 10)
208    }
209    #[doc = "Bit 11 - BOD33 Synchronization Ready Interrupt Enable"]
210    #[inline(always)]
211    #[must_use]
212    pub fn b33srdy(&mut self) -> B33srdyW<IntensetSpec> {
213        B33srdyW::new(self, 11)
214    }
215    #[doc = "Bit 15 - DPLL Lock Rise Interrupt Enable"]
216    #[inline(always)]
217    #[must_use]
218    pub fn dplllckr(&mut self) -> DplllckrW<IntensetSpec> {
219        DplllckrW::new(self, 15)
220    }
221    #[doc = "Bit 16 - DPLL Lock Fall Interrupt Enable"]
222    #[inline(always)]
223    #[must_use]
224    pub fn dplllckf(&mut self) -> DplllckfW<IntensetSpec> {
225        DplllckfW::new(self, 16)
226    }
227    #[doc = "Bit 17 - DPLL Lock Timeout Interrupt Enable"]
228    #[inline(always)]
229    #[must_use]
230    pub fn dplllto(&mut self) -> DpllltoW<IntensetSpec> {
231        DpllltoW::new(self, 17)
232    }
233}
234#[doc = "Interrupt Enable Set\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
235pub struct IntensetSpec;
236impl crate::RegisterSpec for IntensetSpec {
237    type Ux = u32;
238}
239#[doc = "`read()` method returns [`intenset::R`](R) reader structure"]
240impl crate::Readable for IntensetSpec {}
241#[doc = "`write(|w| ..)` method takes [`intenset::W`](W) writer structure"]
242impl crate::Writable for IntensetSpec {
243    type Safety = crate::Unsafe;
244    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
245    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
246}
247#[doc = "`reset()` method sets INTENSET to value 0"]
248impl crate::Resettable for IntensetSpec {
249    const RESET_VALUE: u32 = 0;
250}
atsamd11d/sysctrl/intenset.rs

atsamd11d/sysctrl/
intenset.rs
