Struct atsamd_hal::clock::v2::Enabled

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pub struct Enabled<T, N = U0>(_, _);
Expand description

An enabled, 1:N clock with a compile-time counter for N

This struct is a wrapper around other clock types from this module. It represents a clock, T, that has been enabled, and it maintains a compile-time counter, N, of its consumer clocks in the clock tree.

Compile-time counting allows the API to restrict when clocks may be modified or disabled. For example, Enabled clocks can only be disabled when their counter is U0.

The type-level counter is implemented using Unsigned integers from the typenum crate, and it is modified using the Increment and Decrement traits.

See the Enabled wrapper documentation for more details.

Implementations

Disable the Dfll

Change the Dfll Mode while it remains enabled

Take ownership of an EnabledDfll and convert it to use a new Mode. This requires an instance of the new Mode type and returns an instance of the old Mode type. Users can also supply a closure to alter the Dfll settings before they are applied. The closure takes &mut Dfll<T> as its input, so it can only modify those settings with a set_ method.

See the dfll module documentation for more details on why and how this function would be used.

Disable the Dpll

This method is only implemented for N = U0, which means the clock can only be disabled when no other clocks consume this Dpll.

Test whether the Dpll is locked

Test whether the Dpll is ready

Disable the Gclk

This method is only implemented for N = U0, which means the clock can only be disabled when no other clocks consume this Gclk.

Special methods for an Enabled Gclk0

Gclk0 is special, because it drives the processor’s main clock, which can never be disabled. As discussed in the module-level documentation, this fact is represented by permanently Incrementing the counter for EnabledGclk0. Thus, the minimum value for N is U1 and EnabledGclk0 can never be disabled.

These methods represent actions that can be taken when N = U1, i.e. the Enabled counter is at its minimum value. This is the only time it’s safe to change the Gclk0 Source or change its GclkDivider value.

Swap Gclk0 from one clock Source to another

Gclk0 will remain fully enabled during the swap.

Swap Gclk0 from one GclkIo Pin to another

Gclk0 will remain fully enabled during the swap.

Swap Gclk0 from a clock Source to a GclkIo Pin

Gclk0 will remain fully enabled during the swap.

Swap Gclk0 from a GclkIo Pin to a clock Source

Gclk0 will remain fully enabled during the swap.

Set the GclkDivider value for Gclk0

See Gclk::div documentation for more details.

Output a 50-50 duty cycle clock when using an odd GclkDivider

Return the Gclk0 frequency

See Gclk::freq documentation for more details.

Set the state of GclkOut pins when GclkIo output is disabled

See Gclk::output_off_value documentation for more details.

Create and enable a GclkOut

Enabling GclkIo output will Increment the EnabledGclk counter, which will prevent it from being disabled while the GclkOut exists.

Note that a given Gclk can only use GclkIo for input or output, but not both simultaneously. The NotGclkIo trait exists to enforce this requirement.

Finally, when a GclkOut is disabled, but the Pin is still in AlternateM mode, it takes the “output off value” of the Gclk. See the Gclk::output_off_value documentation for more details.

Disable a GclkOut and free its Pin

Disabling GclkIo output will Decrement the EnabledGclk counter. When a GclkOut is disabled, but the Pin is still in AlternateM mode, it takes the “output off value” of the Gclk. See the Gclk::output_off_value documentation for more details.

Override the factory-default calibration value

Freeze the OSCULP32K configuration until power-on reset

This function sets the write-lock bit, which freezes the OSCULP32K configuration at the hardware level until power-on reset. At the API level, it also consumes and drops the OscUlp32kBase clock, which prevents any further modifications.

Disable 1 kHz output from the OscUlp32kBase clock

This will Decrement the EnabledOscUlp32kBase counter.

Disable 32 kHz output from the OscUlp32kBase clock

This will Decrement the EnabledOscUlp32kBase counter.

Disable the Xosc

This method is only implemented for N = U0, which means the clock can only be disabled when no other clocks consume this Xosc.

Check whether the Xosc is stable and ready to be used as a clock Source

Enable continuous monitoring of the Xosc for clock failure

Failure detection will continuously monitor the Xosc to verify it is still running. In the event of a failure, the Xosc output will be switched to the “safe clock”.

The safe clock is derived from the DFLL, which runs at 48 MHz. The XOSC peripheral provides a prescaler to divide down the 48 MHz DFLL to better match the clock it replaces. The prescaler division factor can be any power of two, 2^N, with N in the range 0..16.

For example, if the Xosc input frequency is 16 MHz, a reasonable divider would be 4, becuase the safe clock frequency would be 12 MHz, which is closest to 16 MHz.

Note that clock failure is triggered when four safe clock periods pass without seeing a rising & falling edge pair on the XOSC clock. Once failure is detected, the corresponding bit in the STATUS register will go high and an interrupt will be triggered.

If the external clock can be fixed, the Xosc can be switched back to it using EnabledXosc::switch_back.

Because the safe clock makes use of the DFLL, the Xosc must register as a consumer of the EnabledDfll and Increment its counter.

Check whether the Xosc has triggered clock failure detection

Failure detection must be enabled for this to return true. Failure is triggered when four safe clock periods pass without seeing a rising & falling edge pair on the XOSC clock.

See EnabledXosc::enable_failure_detection for more details.

Check whether the Xosc has been switched to the safe clock

Returns true if the Xosc has been switched to the safe clock. This will only occur if clock failure detection is enabled.

Attempt to switch from the safe clock back to the external clock

This function will set the switch back bit (SWBEN) in the XOSCCTRL register. Once the hardware has successfully switched back, this bit will be automatically cleared.

Users can check whether switching back was successful by checking the STATUS register with EnabledXosc::is_switched.

Disable continuous monitoring of the Xosc for clock failure

Once failure monitoring is disabled, the DFLL is no longer used as the safe clock, so the EnabledDfll counter can be Decremented.

Disable the Xosc32kBase clock

This method is only implemented for N = U0, which means the clock can only be disabled when no other clocks consume this Xosc32kBase clock.

Check whether the XOSC32K is stable and ready to be used as a clock Source

Freeze the XOSC32K configuration until power-on reset

This function sets the write-lock bit, which freezes the XOSC32K configuration at the hardware level until power-on reset. At the API level, it also consumes and drops the Xosc32kBase clock, which prevents any further modifications.

Disable 1 kHz output from the Xosc32kBase clock

This will Decrement the EnabledXosc32kBase counter.

Disable 1 kHz output from the Xosc32kBase clock

This will Decrement the EnabledXosc32kBase counter.

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