Module atsamd_hal::clock::v2::pclk

Expand description

Peripheral Channel Clocks

Overview

Peripheral channel clocks, or Pclks, connect generic clock controllers (Gclks) to various peripherals within the chip. Each Pclk maps 1:1 with a corresponding peripheral.

The 48 possible Pclks are distinguished by their corresponding PclkId types. Ideally, each PclkId type would be a relevant type from a corresponding HAL module. For example, each of the eight different Sercom types implements PclkId. However, the HAL does not yet support all peripherals, nor have all existing HAL peripherals been integrated with clock::v2. In those cases, a dummy type is defined in the clock::v2::types module.

Pclks are typically leaves in the clock tree. The only exceptions are Pclks used for the DFLL or DPLL peripherals. In those cases, the Pclk acts as a branch clock.

Each Pclk powers only a single peripheral; they do not act as general purpose clock Sources for other clocks in the tree. As a result, they do not need to be wrapped with Enabled.

Pclks also do not have any meaningful configuration beyond identifying which EnabledGclk is its Source. Consequently, PclkTokens can be directly converted into enabled Pclks with Pclk::enable.

See the clock module documentation for a more thorough explanation of the various concepts discussed above.

Example

The following example shows how to enable the Pclk for Sercom0. It derives the Sercom0 clock from EnabledGclk0, which is already running at power-on reset. In doing so, the EnabledGclk0 counter is Incremented.

use atsamd_hal::{
    clock::v2::{clock_system_at_reset, pclk::Pclk},
    pac::Peripherals,
};
let mut pac = Peripherals::take().unwrap();
let (buses, clocks, tokens) = clock_system_at_reset(
    pac.OSCCTRL,
    pac.OSC32KCTRL,
    pac.GCLK,
    pac.MCLK,
    &mut pac.NVMCTRL,
);
let (pclk_sercom0, gclk0) = Pclk::enable(tokens.pclks.sercom0, clocks.gclk0);