Enum atsamd_hal::clock::v2::xosc::SafeClockDiv

#[repr(u8)]
pub enum SafeClockDiv {
    Div1,
    Div2,
    Div4,
    Div8,
    Div16,
    Div32,
    Div64,
    Div128,
    Div256,
    Div512,
    Div1024,
    Div2048,
    Div4096,
    Div8192,
    Div16384,
    Div32768,
}

Division factor for the safe clock prescaler

If an Xosc clock failure is detected, the hardware will switch to a safe clock derived from the Dfll. This enum sets the divider between the 48 MHz DFLL and the safe clock frequency. The divider can be any value of 2^N, with N in the range 0..16.

Variants

Div1

Div2

Div4

Div8

Div16

Div32

Div64

Div128

Div256

Div512

Div1024

Div2048

Div4096

Div8192

Div16384

Div32768

Trait Implementations

impl Clone for SafeClockDiv

fn clone(&self) -> SafeClockDiv

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for SafeClockDiv

fn default() -> SafeClockDiv

Returns the “default value” for a type.

impl PartialEq<SafeClockDiv> for SafeClockDiv

fn eq(&self, other: &SafeClockDiv) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for SafeClockDiv

impl Eq for SafeClockDiv

impl StructuralEq for SafeClockDiv

impl StructuralPartialEq for SafeClockDiv