Trait atsamd_hal::clock::v2::gclk::GclkDivider
source · [−]pub trait GclkDivider: Sealed + Default + Copy {
fn divider(&self) -> u32;
fn divsel_div(&self) -> (DIVSEL_A, u16);
}
Expand description
Trait unifying the two Gclk
divider types, GclkDiv8
and
GclkDiv16
Choosing a Gclk
division factor can be complicated. Gclk1
can accept
a 16-bit divider value, while all other Gclk
s only take an 8-bit value.
Moreover, the set of valid clock dividers does not form a contiguous range.
For example, the valid set of dividers for most Gclk
s is 1-256 and 512.
The GclkDiv8
and GclkDiv16
enums provide simple and intuitive
user-facing interfaces to choose the actual clock divider value. This
trait, on the other hand, provides an internal-facing interface used by HAL
authors to extract the clock divider and convert it to the corresponding
DIVSEL
and DIV
register fields. Users should have no reason to interact
with this trait directly.
Required Methods
sourcefn divsel_div(&self) -> (DIVSEL_A, u16)
fn divsel_div(&self) -> (DIVSEL_A, u16)
Return the corresponding DIVSEL
and and DIV
register fields