pub struct Spi<C, A>where
C: ValidConfig,
A: Capability,{ /* private fields */ }
Expand description
An enabled SPI peripheral that can perform transactions
See the impl_ehal
documentation for details on the implementations of
the embedded HAL traits, which vary based on Size
and Capability
.
Implementations
sourceimpl<C, A> Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> Spi<C, A>where
C: ValidConfig,
A: Capability,
sourcepub fn length<L: Length>(self) -> Spi<Config<C::Pads, C::OpMode, L>, A>where
Config<C::Pads, C::OpMode, L>: ValidConfig,
pub fn length<L: Length>(self) -> Spi<Config<C::Pads, C::OpMode, L>, A>where
Config<C::Pads, C::OpMode, L>: ValidConfig,
sourcepub fn reconfigure(&mut self, update: impl FnOnce(&mut SpecificConfig<C>))
pub fn reconfigure(&mut self, update: impl FnOnce(&mut SpecificConfig<C>))
Update the SPI configuration.
Calling this method will temporarily disable the SERCOM peripheral, as some registers are enable-protected. This may interrupt any ongoing transactions.
sourcepub fn enable_interrupts(&mut self, flags: Flags)
pub fn enable_interrupts(&mut self, flags: Flags)
Enable interrupts for the specified flags
sourcepub fn disable_interrupts(&mut self, flags: Flags)
pub fn disable_interrupts(&mut self, flags: Flags)
Disable interrupts for the specified flags
sourcepub fn read_flags(&self) -> Flags
pub fn read_flags(&self) -> Flags
Read the interrupt flags
sourcepub fn clear_flags(&mut self, flags: Flags)
pub fn clear_flags(&mut self, flags: Flags)
Clear the corresponding interrupt flags
Only the ERROR, SSL and TXC flags can be cleared.
Note: The implementation of of serial::Write::flush
waits on and
clears the TXC
flag. Manually clearing this flag could cause it to
hang indefinitely.
sourcepub fn read_status(&self) -> Status
pub fn read_status(&self) -> Status
Read the error status flags
sourcepub fn clear_status(&mut self, status: Status)
pub fn clear_status(&mut self, status: Status)
Clear the corresponding error status flags
sourcepub fn read_flags_errors(&self) -> Result<Flags, Error>
pub fn read_flags_errors(&self) -> Result<Flags, Error>
Try to read the interrupt flags, but first check the error status flags.
sourcepub unsafe fn read_data(&mut self) -> DataWidth
pub unsafe fn read_data(&mut self) -> DataWidth
Read from the DATA register
Reading from the data register directly is unsafe
, because it will
clear the RXC flag, which could break assumptions made elsewhere in
this module.
sourcepub unsafe fn write_data(&mut self, data: DataWidth)
pub unsafe fn write_data(&mut self, data: DataWidth)
Write to the DATA register
Writing to the data register directly is unsafe
, because it will clear
the DRE flag, which could break assumptions made elsewhere in this
module.
sourceimpl<P, M, A> Spi<Config<P, M, DynLength>, A>where
P: ValidPads,
M: OpMode,
Config<P, M, DynLength>: ValidConfig,
A: Capability,
impl<P, M, A> Spi<Config<P, M, DynLength>, A>where
P: ValidPads,
M: OpMode,
Config<P, M, DynLength>: ValidConfig,
A: Capability,
sourcepub fn get_dyn_length(&self) -> u8
pub fn get_dyn_length(&self) -> u8
Return the current transaction length
Read the LENGTH register to determine the current transaction length
sourcepub fn set_dyn_length(&mut self, length: u8)
pub fn set_dyn_length(&mut self, length: u8)
Set the transaction length
Write the LENGTH register to set the transaction length. Panics if the length is zero.
Changing the transaction LENGTH
while is enabled is permissible but
dangerous. If you have sent or received any bytes at the current
LENGTH
, you must wait for a TXC flag before changing to a new
LENGTH
.
Trait Implementations
sourceimpl<C, A> AnySpi for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AnySpi for Spi<C, A>where
C: ValidConfig,
A: Capability,
sourceimpl<C, A> AsMut<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AsMut<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
sourceimpl<C, A> AsRef<Config<<C as AnyConfig>::Pads, <C as AnyConfig>::OpMode, <C as AnyConfig>::Size>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AsRef<Config<<C as AnyConfig>::Pads, <C as AnyConfig>::OpMode, <C as AnyConfig>::Size>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
Get a shared reference to the underlying Config
struct
This can be used to call the various get_*
functions on Config
sourcefn as_ref(&self) -> &SpecificConfig<C>
fn as_ref(&self) -> &SpecificConfig<C>
sourceimpl<C, A> AsRef<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AsRef<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
sourceimpl<P, M, A> CheckBufLen for Spi<Config<P, M, DynLength>, A>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Capability,
impl<P, M, A> CheckBufLen for Spi<Config<P, M, DynLength>, A>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Capability,
sourcefn check_buf_len(&self, buf: &impl AsRef<[u8]>)
fn check_buf_len(&self, buf: &impl AsRef<[u8]>)
sourceimpl<P, M, L, A> CheckBufLen for Spi<Config<P, M, L>, A>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: StaticLength,
A: Capability,
impl<P, M, L, A> CheckBufLen for Spi<Config<P, M, L>, A>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: StaticLength,
A: Capability,
sourcefn check_buf_len(&self, buf: &impl AsRef<[u8]>)
fn check_buf_len(&self, buf: &impl AsRef<[u8]>)
sourceimpl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<u32>,
u32: AsPrimitive<C::Word>,
impl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<u32>,
u32: AsPrimitive<C::Word>,
Implement spi::FullDuplex
for Spi
structs with AtomicSize
spi::FullDuplex
is only implemented when the Spi
struct has Duplex
Capability
and the transaction Length
is <= 4
bytes. When the
Length
is <= 4
, the Word
is a primitive integer, with a size that
depends on the Length
(u8
, u16
or u32
).
sourceimpl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
u32: AsPrimitive<L::Word>,
impl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
u32: AsPrimitive<L::Word>,
Implement serial::Read
for Rx
Spi
structs in a MasterMode
serial::Read
is only implemented for Spi
structs with Rx
Capability
. In a MasterMode
, Read
has to initiate transactions, so
it keeps track of the transaction state. If a transaction is in progress,
it will wait on RXC
. If not, it will wait on DRE
, and then send 0
.
sourceimpl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
u32: AsPrimitive<L::Word>,
impl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
u32: AsPrimitive<L::Word>,
Implement serial::Read
for Rx
Spi
structs in Slave
OpMode
serial::Read
is only implemented for Spi
structs with Rx
Capability
. In Slave
OpMode
, Read
does not have to initiate
transactions, so it does not have to store any internal state. It only has
to wait on RXC
.
sourceimpl<P, M, A> Transfer<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, A>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
impl<P, M, A> Transfer<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, A>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
Implement Transfer
for Spi
structs that can Receive
and have an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, A>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, A>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
Implement Transfer
for Spi
structs that can Receive
and have an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, A>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, A>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
Implement Transfer
for Spi
structs that can Receive
and have an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M, A> Transfer<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, A>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
impl<P, M, A> Transfer<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, A>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
Implement Transfer
for Spi
structs that can Receive
and have an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M, A> Transfer<u8> for Spi<Config<P, M, DynLength>, A>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
impl<P, M, A> Transfer<u8> for Spi<Config<P, M, DynLength>, A>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
A: Receive,
Implement Transfer
for Spi
structs that can Receive
and have
DynLength
The transfer accepts a slice of u8
with a length equal to the run-time
dynamic transaction length. If the slice length does not match the result
of Spi::get_dyn_length
, it will panic.
sourceimpl<P, M, L, A> Transfer<u8> for Spi<Config<P, M, L>, A>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
A: Receive,
impl<P, M, L, A> Transfer<u8> for Spi<Config<P, M, L>, A>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
A: Receive,
sourceimpl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<u32>,
impl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<u32>,
Implement serial::Write
for Tx
Spi
structs
serial::Write
is only implemented for Spi
structs with Tx
Capability
. Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and
DynLength
The transfer accepts a [u8]
with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length
, it will panic.
sourceimpl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and
DynLength
The transfer accepts a [u8]
with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length
], it will panic.
Because the Capability
is Tx
, this implementation never reads the DATA
register and ignores all buffer overflow errors.
sourceimpl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
sourceimpl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
Implement Write
for Spi
structs with Tx
Capability
and long
transaction Length
s
The transaction Length
must be > 4
. The transfer accepts a [u8]
with
a length equal to the transfer Length
. If the slice length is incorrect,
it will panic.
Because the Capability
is Tx
, this implementation never reads the DATA
register and ignores all buffer overflow errors.
sourceimpl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U4>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U4>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U4>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U4>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U2>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U2>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U2>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U2>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U3>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U3>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U3>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U3>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U1>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U1>>,
words
to the slave, ignoring all the incoming wordssourceimpl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement WriteIter
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourcefn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U1>>,
fn write_iter<WI>(&mut self, words: WI) -> Result<(), Error>where
WI: IntoIterator<Item = Word<U1>>,
words
to the slave, ignoring all the incoming words