pub trait _embedded_hal_blocking_spi_Write<W> {
type Error;
fn write(&mut self, words: &[W]) -> Result<(), Self::Error>;
}
Expand description
Blocking write
Required Associated Types
Required Methods
Implementors
sourceimpl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>where
Config<P, M, U4>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>where
Config<P, M, U2>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>where
Config<P, M, U3>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
sourceimpl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>where
Config<P, M, U1>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and an AtomicSize
The transaction Length
must be <= 4
. The transfer accepts
a slice of primitive integers, depending on the Length
(u8
, u16
or u32
).
Because the Capability
is Tx
, this implementation never
reads the DATA register and ignores all buffer overflow errors.
sourceimpl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Duplex
Capability
and
DynLength
The transfer accepts a [u8]
with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length
, it will panic.
sourceimpl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>where
Config<P, M, DynLength>: ValidConfig,
P: ValidPads,
M: OpMode,
Implement Write
for Spi
structs with Tx
Capability
and
DynLength
The transfer accepts a [u8]
with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length
], it will panic.
Because the Capability
is Tx
, this implementation never reads the DATA
register and ignores all buffer overflow errors.
sourceimpl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
sourceimpl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: OpMode,
L: GreaterThan4,
Implement Write
for Spi
structs with Tx
Capability
and long
transaction Length
s
The transaction Length
must be > 4
. The transfer accepts a [u8]
with
a length equal to the transfer Length
. If the slice length is incorrect,
it will panic.
Because the Capability
is Tx
, this implementation never reads the DATA
register and ignores all buffer overflow errors.