Trait embedded_hal::blocking::i2c::TransactionalIter   
source · [−]pub trait TransactionalIter<A: AddressMode = SevenBitAddress> {
    type Error;
    fn exec_iter<'a, O>(
        &mut self,
        address: A,
        operations: O
    ) -> Result<(), Self::Error>
    where
        O: IntoIterator<Item = Operation<'a>>;
}Expand description
Transactional I2C interface (iterator version).
This allows combining operation within an I2C transaction.
Required Associated Types
Required Methods
sourcefn exec_iter<'a, O>(
    &mut self,
    address: A,
    operations: O
) -> Result<(), Self::Error>where
    O: IntoIterator<Item = Operation<'a>>,
 
fn exec_iter<'a, O>(
    &mut self,
    address: A,
    operations: O
) -> Result<(), Self::Error>where
    O: IntoIterator<Item = Operation<'a>>,
Execute the provided operations on the I2C bus (iterator version).
Transaction contract:
- 
Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate. 
- 
Data from adjacent operations of the same type are sent after each other without an SP or SR. 
- 
Between adjacent operations of a different type an SR and SAD+R/W is sent. 
- 
After executing the last operation an SP is sent automatically. 
- 
If the last operation is a Readthe master does not send an acknowledge for the last byte.
- 
ST= start condition
- 
SAD+R/W= slave address followed by bit 1 to indicate reading or 0 to indicate writing
- 
SR= repeated start condition
- 
SP= stop condition