Enum atsamd51n::dmac::channel::chctrla::TRIGSRC_A

source · [−]

#[repr(u8)]
pub enum TRIGSRC_A {
Show 85 variants    DISABLE,
    RTC_TIMESTAMP,
    DSU_DCC0,
    DSU_DCC1,
    SERCOM0_RX,
    SERCOM0_TX,
    SERCOM1_RX,
    SERCOM1_TX,
    SERCOM2_RX,
    SERCOM2_TX,
    SERCOM3_RX,
    SERCOM3_TX,
    SERCOM4_RX,
    SERCOM4_TX,
    SERCOM5_RX,
    SERCOM5_TX,
    SERCOM6_RX,
    SERCOM6_TX,
    SERCOM7_RX,
    SERCOM7_TX,
    CAN0_DEBUG,
    CAN1_DEBUG,
    TCC0_OVF,
    TCC0_MC_0,
    TCC0_MC_1,
    TCC0_MC_2,
    TCC0_MC_3,
    TCC0_MC_4,
    TCC0_MC_5,
    TCC1_OVF,
    TCC1_MC_0,
    TCC1_MC_1,
    TCC1_MC_2,
    TCC1_MC_3,
    TCC2_OVF,
    TCC2_MC_0,
    TCC2_MC_1,
    TCC2_MC_2,
    TCC3_OVF,
    TCC3_MC_0,
    TCC3_MC_1,
    TCC4_OVF,
    TCC4_MC_0,
    TCC4_MC_1,
    TC0_OVF,
    TC0_MC_0,
    TC0_MC_1,
    TC1_OVF,
    TC1_MC_0,
    TC1_MC_1,
    TC2_OVF,
    TC2_MC_0,
    TC2_MC_1,
    TC3_OVF,
    TC3_MC_0,
    TC3_MC_1,
    TC4_OVF,
    TC4_MC_0,
    TC4_MC_1,
    TC5_OVF,
    TC5_MC_0,
    TC5_MC_1,
    TC6_OVF,
    TC6_MC_0,
    TC6_MC_1,
    TC7_OVF,
    TC7_MC_0,
    TC7_MC_1,
    ADC0_RESRDY,
    ADC0_SEQ,
    ADC1_RESRDY,
    ADC1_SEQ,
    DAC_EMPTY_0,
    DAC_EMPTY_1,
    DAC_RESRDY_0,
    DAC_RESRDY_1,
    I2S_RX_0,
    I2S_RX_1,
    I2S_TX_0,
    I2S_TX_1,
    PCC_RX,
    AES_WR,
    AES_RD,
    QSPI_RX,
    QSPI_TX,
}

Expand description

Trigger Source

Value on reset: 0

Variants

`DISABLE`

0: Only software/event triggers

`RTC_TIMESTAMP`

1: DMA RTC timestamp trigger

`DSU_DCC0`

2: DMAC ID for DCC0 register

`DSU_DCC1`

3: DMAC ID for DCC1 register

`SERCOM0_RX`

4: Index of DMA RX trigger

`SERCOM0_TX`

5: Index of DMA TX trigger

`SERCOM1_RX`

6: Index of DMA RX trigger

`SERCOM1_TX`

7: Index of DMA TX trigger

`SERCOM2_RX`

8: Index of DMA RX trigger

`SERCOM2_TX`

9: Index of DMA TX trigger

`SERCOM3_RX`

10: Index of DMA RX trigger

`SERCOM3_TX`

11: Index of DMA TX trigger

`SERCOM4_RX`

12: Index of DMA RX trigger

`SERCOM4_TX`

13: Index of DMA TX trigger

`SERCOM5_RX`

14: Index of DMA RX trigger

`SERCOM5_TX`

15: Index of DMA TX trigger

`SERCOM6_RX`

16: Index of DMA RX trigger

`SERCOM6_TX`

17: Index of DMA TX trigger

`SERCOM7_RX`

18: Index of DMA RX trigger

`SERCOM7_TX`

19: Index of DMA TX trigger

`CAN0_DEBUG`

20: DMA CAN Debug Req

`CAN1_DEBUG`

21: DMA CAN Debug Req

`TCC0_OVF`

22: DMA overflow/underflow/retrigger trigger

`TCC0_MC_0`

23: Indexes of DMA Match/Compare triggers

`TCC0_MC_1`

24: Indexes of DMA Match/Compare triggers

`TCC0_MC_2`

25: Indexes of DMA Match/Compare triggers

`TCC0_MC_3`

26: Indexes of DMA Match/Compare triggers

`TCC0_MC_4`

27: Indexes of DMA Match/Compare triggers

`TCC0_MC_5`

28: Indexes of DMA Match/Compare triggers

`TCC1_OVF`

29: DMA overflow/underflow/retrigger trigger

`TCC1_MC_0`

30: Indexes of DMA Match/Compare triggers

`TCC1_MC_1`

31: Indexes of DMA Match/Compare triggers

`TCC1_MC_2`

32: Indexes of DMA Match/Compare triggers

`TCC1_MC_3`

33: Indexes of DMA Match/Compare triggers

`TCC2_OVF`

34: DMA overflow/underflow/retrigger trigger

`TCC2_MC_0`

35: Indexes of DMA Match/Compare triggers

`TCC2_MC_1`

36: Indexes of DMA Match/Compare triggers

`TCC2_MC_2`

37: Indexes of DMA Match/Compare triggers

`TCC3_OVF`

38: DMA overflow/underflow/retrigger trigger

`TCC3_MC_0`

39: Indexes of DMA Match/Compare triggers

`TCC3_MC_1`

40: Indexes of DMA Match/Compare triggers

`TCC4_OVF`

41: DMA overflow/underflow/retrigger trigger

`TCC4_MC_0`

42: Indexes of DMA Match/Compare triggers

`TCC4_MC_1`

43: Indexes of DMA Match/Compare triggers

`TC0_OVF`

44: Indexes of DMA Overflow trigger

`TC0_MC_0`

45: Indexes of DMA Match/Compare triggers

`TC0_MC_1`

46: Indexes of DMA Match/Compare triggers

`TC1_OVF`

47: Indexes of DMA Overflow trigger

`TC1_MC_0`

48: Indexes of DMA Match/Compare triggers

`TC1_MC_1`

49: Indexes of DMA Match/Compare triggers

`TC2_OVF`

50: Indexes of DMA Overflow trigger

`TC2_MC_0`

51: Indexes of DMA Match/Compare triggers

`TC2_MC_1`

52: Indexes of DMA Match/Compare triggers

`TC3_OVF`

53: Indexes of DMA Overflow trigger

`TC3_MC_0`

54: Indexes of DMA Match/Compare triggers

`TC3_MC_1`

55: Indexes of DMA Match/Compare triggers

`TC4_OVF`

56: Indexes of DMA Overflow trigger

`TC4_MC_0`

57: Indexes of DMA Match/Compare triggers

`TC4_MC_1`

58: Indexes of DMA Match/Compare triggers

`TC5_OVF`

59: Indexes of DMA Overflow trigger

`TC5_MC_0`

60: Indexes of DMA Match/Compare triggers

`TC5_MC_1`

61: Indexes of DMA Match/Compare triggers

`TC6_OVF`

62: Indexes of DMA Overflow trigger

`TC6_MC_0`

63: Indexes of DMA Match/Compare triggers

`TC6_MC_1`

64: Indexes of DMA Match/Compare triggers

`TC7_OVF`

65: Indexes of DMA Overflow trigger

`TC7_MC_0`

66: Indexes of DMA Match/Compare triggers

`TC7_MC_1`

67: Indexes of DMA Match/Compare triggers

`ADC0_RESRDY`

68: index of DMA RESRDY trigger

`ADC0_SEQ`

69: Index of DMA SEQ trigger

`ADC1_RESRDY`

70: Index of DMA RESRDY trigger

`ADC1_SEQ`

71: Index of DMA SEQ trigger

`DAC_EMPTY_0`

72: DMA DAC Empty Req

`DAC_EMPTY_1`

73: DMA DAC Empty Req

`DAC_RESRDY_0`

74: DMA DAC Result Ready Req

`DAC_RESRDY_1`

75: DMA DAC Result Ready Req

`I2S_RX_0`

76: Indexes of DMA RX triggers

`I2S_RX_1`

77: Indexes of DMA RX triggers

`I2S_TX_0`

78: Indexes of DMA TX triggers

`I2S_TX_1`

79: Indexes of DMA TX triggers

`PCC_RX`

80: Indexes of PCC RX trigger

`AES_WR`

81: DMA DATA Write trigger

`AES_RD`

82: DMA DATA Read trigger

`QSPI_RX`

83: Indexes of QSPI RX trigger

`QSPI_TX`

84: Indexes of QSPI TX trigger

Trait Implementations

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impl Clone for TRIGSRC_A

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fn clone(&self) -> TRIGSRC_A

Returns a copy of the value. Read more

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more

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impl Copy for TRIGSRC_A

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impl StructuralPartialEq for TRIGSRC_A

Auto Trait Implementations

impl RefUnwindSafe for TRIGSRC_A

impl Send for TRIGSRC_A

impl Sync for TRIGSRC_A

impl Unpin for TRIGSRC_A

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source

impl<T, U> TryFrom for Twhere
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

const: unstable · source

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

source

impl<T, U> TryInto for Twhere
U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.

const: unstable · source

fn try_into(self) -> Result<U, >::Error>

Performs the conversion.