Struct atsamd51g::etm::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 40 fields
pub cr: Reg<CR_SPEC>,
pub ccr: Reg<CCR_SPEC>,
pub trigger: Reg<TRIGGER_SPEC>,
pub sr: Reg<SR_SPEC>,
pub scr: Reg<SCR_SPEC>,
pub teevr: Reg<TEEVR_SPEC>,
pub tecr1: Reg<TECR1_SPEC>,
pub fflr: Reg<FFLR_SPEC>,
pub cntrldvr1: Reg<CNTRLDVR1_SPEC>,
pub syncfr: Reg<SYNCFR_SPEC>,
pub idr: Reg<IDR_SPEC>,
pub ccer: Reg<CCER_SPEC>,
pub tesseicr: Reg<TESSEICR_SPEC>,
pub tsevt: Reg<TSEVT_SPEC>,
pub traceidr: Reg<TRACEIDR_SPEC>,
pub idr2: Reg<IDR2_SPEC>,
pub pdsr: Reg<PDSR_SPEC>,
pub itmiscin: Reg<ITMISCIN_SPEC>,
pub ittrigout: Reg<ITTRIGOUT_SPEC>,
pub itatbctr2: Reg<ITATBCTR2_SPEC>,
pub itatbctr0: Reg<ITATBCTR0_SPEC>,
pub itctrl: Reg<ITCTRL_SPEC>,
pub claimset: Reg<CLAIMSET_SPEC>,
pub claimclr: Reg<CLAIMCLR_SPEC>,
pub lar: Reg<LAR_SPEC>,
pub lsr: Reg<LSR_SPEC>,
pub authstatus: Reg<AUTHSTATUS_SPEC>,
pub devtype: Reg<DEVTYPE_SPEC>,
pub pidr4: Reg<PIDR4_SPEC>,
pub pidr5: Reg<PIDR5_SPEC>,
pub pidr6: Reg<PIDR6_SPEC>,
pub pidr7: Reg<PIDR7_SPEC>,
pub pidr0: Reg<PIDR0_SPEC>,
pub pidr1: Reg<PIDR1_SPEC>,
pub pidr2: Reg<PIDR2_SPEC>,
pub pidr3: Reg<PIDR3_SPEC>,
pub cidr0: Reg<CIDR0_SPEC>,
pub cidr1: Reg<CIDR1_SPEC>,
pub cidr2: Reg<CIDR2_SPEC>,
pub cidr3: Reg<CIDR3_SPEC>,
/* private fields */
}Expand description
Register block
Fields
cr: Reg<CR_SPEC>0x00 - ETM Main Control Register
ccr: Reg<CCR_SPEC>0x04 - ETM Configuration Code Register
trigger: Reg<TRIGGER_SPEC>0x08 - ETM Trigger Event Register
sr: Reg<SR_SPEC>0x10 - ETM Status Register
scr: Reg<SCR_SPEC>0x14 - ETM System Configuration Register
teevr: Reg<TEEVR_SPEC>0x20 - ETM TraceEnable Event Register
tecr1: Reg<TECR1_SPEC>0x24 - ETM TraceEnable Control 1 Register
fflr: Reg<FFLR_SPEC>0x28 - ETM FIFO Full Level Register
cntrldvr1: Reg<CNTRLDVR1_SPEC>0x140 - ETM Free-running Counter Reload Value
syncfr: Reg<SYNCFR_SPEC>0x1e0 - ETM Synchronization Frequency Register
idr: Reg<IDR_SPEC>0x1e4 - ETM ID Register
ccer: Reg<CCER_SPEC>0x1e8 - ETM Configuration Code Extension Register
tesseicr: Reg<TESSEICR_SPEC>0x1f0 - ETM TraceEnable Start/Stop EmbeddedICE Control Register
tsevt: Reg<TSEVT_SPEC>0x1f8 - ETM TimeStamp Event Register
traceidr: Reg<TRACEIDR_SPEC>0x200 - ETM CoreSight Trace ID Register
idr2: Reg<IDR2_SPEC>0x208 - ETM ID Register 2
pdsr: Reg<PDSR_SPEC>0x314 - ETM Device Power-Down Status Register
itmiscin: Reg<ITMISCIN_SPEC>0xee0 - ETM Integration Test Miscellaneous Inputs
ittrigout: Reg<ITTRIGOUT_SPEC>0xee8 - ETM Integration Test Trigger Out
itatbctr2: Reg<ITATBCTR2_SPEC>0xef0 - ETM Integration Test ATB Control 2
itatbctr0: Reg<ITATBCTR0_SPEC>0xef8 - ETM Integration Test ATB Control 0
itctrl: Reg<ITCTRL_SPEC>0xf00 - ETM Integration Mode Control Register
claimset: Reg<CLAIMSET_SPEC>0xfa0 - ETM Claim Tag Set Register
claimclr: Reg<CLAIMCLR_SPEC>0xfa4 - ETM Claim Tag Clear Register
lar: Reg<LAR_SPEC>0xfb0 - ETM Lock Access Register
lsr: Reg<LSR_SPEC>0xfb4 - ETM Lock Status Register
authstatus: Reg<AUTHSTATUS_SPEC>0xfb8 - ETM Authentication Status Register
devtype: Reg<DEVTYPE_SPEC>0xfcc - ETM CoreSight Device Type Register
pidr4: Reg<PIDR4_SPEC>0xfd0 - ETM Peripheral Identification Register #4
pidr5: Reg<PIDR5_SPEC>0xfd4 - ETM Peripheral Identification Register #5
pidr6: Reg<PIDR6_SPEC>0xfd8 - ETM Peripheral Identification Register #6
pidr7: Reg<PIDR7_SPEC>0xfdc - ETM Peripheral Identification Register #7
pidr0: Reg<PIDR0_SPEC>0xfe0 - ETM Peripheral Identification Register #0
pidr1: Reg<PIDR1_SPEC>0xfe4 - ETM Peripheral Identification Register #1
pidr2: Reg<PIDR2_SPEC>0xfe8 - ETM Peripheral Identification Register #2
pidr3: Reg<PIDR3_SPEC>0xfec - ETM Peripheral Identification Register #3
cidr0: Reg<CIDR0_SPEC>0xff0 - ETM Component Identification Register #0
cidr1: Reg<CIDR1_SPEC>0xff4 - ETM Component Identification Register #1
cidr2: Reg<CIDR2_SPEC>0xff8 - ETM Component Identification Register #2
cidr3: Reg<CIDR3_SPEC>0xffc - ETM Component Identification Register #3