Struct cortex_m::peripheral::scb::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub icsr: RW<u32>,
    pub vtor: RW<u32>,
    pub aircr: RW<u32>,
    pub scr: RW<u32>,
    pub ccr: RW<u32>,
    pub shpr: [RW<u32>; 2],
    pub shcsr: RW<u32>,
    /* private fields */
}

Register block

Fields

icsr: RW<u32>

Interrupt Control and State

vtor: RW<u32>

Vector Table Offset (not present on Cortex-M0 variants)

aircr: RW<u32>

Application Interrupt and Reset Control

scr: RW<u32>

System Control

ccr: RW<u32>

Configuration and Control

shpr: [RW<u32>; 2]

System Handler Priority (word accessible only on Cortex-M0 variants)

On ARMv7-M, shpr[0] points to SHPR1

On ARMv6-M, shpr[0] points to SHPR2

shcsr: RW<u32>

System Handler Control and State