#[repr(C)]pub struct HOST {Show 79 fields
pub ctrla: Reg<CTRLA_SPEC>,
pub syncbusy: Reg<SYNCBUSY_SPEC>,
pub qosctrl: Reg<QOSCTRL_SPEC>,
pub ctrlb: Reg<CTRLB_SPEC>,
pub hsofc: Reg<HSOFC_SPEC>,
pub status: Reg<STATUS_SPEC>,
pub fsmstatus: Reg<FSMSTATUS_SPEC>,
pub fnum: Reg<FNUM_SPEC>,
pub flenhigh: Reg<FLENHIGH_SPEC>,
pub intenclr: Reg<INTENCLR_SPEC>,
pub intenset: Reg<INTENSET_SPEC>,
pub intflag: Reg<INTFLAG_SPEC>,
pub pintsmry: Reg<PINTSMRY_SPEC>,
pub descadd: Reg<DESCADD_SPEC>,
pub padcal: Reg<PADCAL_SPEC>,
pub pcfg0: Reg<PCFG_SPEC>,
pub binterval0: Reg<BINTERVAL_SPEC>,
pub pstatusclr0: Reg<PSTATUSCLR_SPEC>,
pub pstatusset0: Reg<PSTATUSSET_SPEC>,
pub pstatus0: Reg<PSTATUS_SPEC>,
pub pintflag0: Reg<PINTFLAG_SPEC>,
pub pintenclr0: Reg<PINTENCLR_SPEC>,
pub pintenset0: Reg<PINTENSET_SPEC>,
pub pcfg1: Reg<PCFG_SPEC>,
pub binterval1: Reg<BINTERVAL_SPEC>,
pub pstatusclr1: Reg<PSTATUSCLR_SPEC>,
pub pstatusset1: Reg<PSTATUSSET_SPEC>,
pub pstatus1: Reg<PSTATUS_SPEC>,
pub pintflag1: Reg<PINTFLAG_SPEC>,
pub pintenclr1: Reg<PINTENCLR_SPEC>,
pub pintenset1: Reg<PINTENSET_SPEC>,
pub pcfg2: Reg<PCFG_SPEC>,
pub binterval2: Reg<BINTERVAL_SPEC>,
pub pstatusclr2: Reg<PSTATUSCLR_SPEC>,
pub pstatusset2: Reg<PSTATUSSET_SPEC>,
pub pstatus2: Reg<PSTATUS_SPEC>,
pub pintflag2: Reg<PINTFLAG_SPEC>,
pub pintenclr2: Reg<PINTENCLR_SPEC>,
pub pintenset2: Reg<PINTENSET_SPEC>,
pub pcfg3: Reg<PCFG_SPEC>,
pub binterval3: Reg<BINTERVAL_SPEC>,
pub pstatusclr3: Reg<PSTATUSCLR_SPEC>,
pub pstatusset3: Reg<PSTATUSSET_SPEC>,
pub pstatus3: Reg<PSTATUS_SPEC>,
pub pintflag3: Reg<PINTFLAG_SPEC>,
pub pintenclr3: Reg<PINTENCLR_SPEC>,
pub pintenset3: Reg<PINTENSET_SPEC>,
pub pcfg4: Reg<PCFG_SPEC>,
pub binterval4: Reg<BINTERVAL_SPEC>,
pub pstatusclr4: Reg<PSTATUSCLR_SPEC>,
pub pstatusset4: Reg<PSTATUSSET_SPEC>,
pub pstatus4: Reg<PSTATUS_SPEC>,
pub pintflag4: Reg<PINTFLAG_SPEC>,
pub pintenclr4: Reg<PINTENCLR_SPEC>,
pub pintenset4: Reg<PINTENSET_SPEC>,
pub pcfg5: Reg<PCFG_SPEC>,
pub binterval5: Reg<BINTERVAL_SPEC>,
pub pstatusclr5: Reg<PSTATUSCLR_SPEC>,
pub pstatusset5: Reg<PSTATUSSET_SPEC>,
pub pstatus5: Reg<PSTATUS_SPEC>,
pub pintflag5: Reg<PINTFLAG_SPEC>,
pub pintenclr5: Reg<PINTENCLR_SPEC>,
pub pintenset5: Reg<PINTENSET_SPEC>,
pub pcfg6: Reg<PCFG_SPEC>,
pub binterval6: Reg<BINTERVAL_SPEC>,
pub pstatusclr6: Reg<PSTATUSCLR_SPEC>,
pub pstatusset6: Reg<PSTATUSSET_SPEC>,
pub pstatus6: Reg<PSTATUS_SPEC>,
pub pintflag6: Reg<PINTFLAG_SPEC>,
pub pintenclr6: Reg<PINTENCLR_SPEC>,
pub pintenset6: Reg<PINTENSET_SPEC>,
pub pcfg7: Reg<PCFG_SPEC>,
pub binterval7: Reg<BINTERVAL_SPEC>,
pub pstatusclr7: Reg<PSTATUSCLR_SPEC>,
pub pstatusset7: Reg<PSTATUSSET_SPEC>,
pub pstatus7: Reg<PSTATUS_SPEC>,
pub pintflag7: Reg<PINTFLAG_SPEC>,
pub pintenclr7: Reg<PINTENCLR_SPEC>,
pub pintenset7: Reg<PINTENSET_SPEC>,
/* private fields */
}Expand description
Register block
Fields
ctrla: Reg<CTRLA_SPEC>0x00 - Control A
syncbusy: Reg<SYNCBUSY_SPEC>0x02 - Synchronization Busy
qosctrl: Reg<QOSCTRL_SPEC>0x03 - USB Quality Of Service
ctrlb: Reg<CTRLB_SPEC>0x08 - HOST Control B
hsofc: Reg<HSOFC_SPEC>0x0a - HOST Host Start Of Frame Control
status: Reg<STATUS_SPEC>0x0c - HOST Status
fsmstatus: Reg<FSMSTATUS_SPEC>0x0d - Finite State Machine Status
fnum: Reg<FNUM_SPEC>0x10 - HOST Host Frame Number
flenhigh: Reg<FLENHIGH_SPEC>0x12 - HOST Host Frame Length
intenclr: Reg<INTENCLR_SPEC>0x14 - HOST Host Interrupt Enable Clear
intenset: Reg<INTENSET_SPEC>0x18 - HOST Host Interrupt Enable Set
intflag: Reg<INTFLAG_SPEC>0x1c - HOST Host Interrupt Flag
pintsmry: Reg<PINTSMRY_SPEC>0x20 - HOST Pipe Interrupt Summary
descadd: Reg<DESCADD_SPEC>0x24 - Descriptor Address
padcal: Reg<PADCAL_SPEC>0x28 - USB PAD Calibration
pcfg0: Reg<PCFG_SPEC>0x100 - HOST End Point Configuration
binterval0: Reg<BINTERVAL_SPEC>0x103 - HOST Bus Access Period of Pipe
pstatusclr0: Reg<PSTATUSCLR_SPEC>0x104 - HOST End Point Pipe Status Clear
pstatusset0: Reg<PSTATUSSET_SPEC>0x105 - HOST End Point Pipe Status Set
pstatus0: Reg<PSTATUS_SPEC>0x106 - HOST End Point Pipe Status
pintflag0: Reg<PINTFLAG_SPEC>0x107 - HOST Pipe Interrupt Flag
pintenclr0: Reg<PINTENCLR_SPEC>0x108 - HOST Pipe Interrupt Flag Clear
pintenset0: Reg<PINTENSET_SPEC>0x109 - HOST Pipe Interrupt Flag Set
pcfg1: Reg<PCFG_SPEC>0x120 - HOST End Point Configuration
binterval1: Reg<BINTERVAL_SPEC>0x123 - HOST Bus Access Period of Pipe
pstatusclr1: Reg<PSTATUSCLR_SPEC>0x124 - HOST End Point Pipe Status Clear
pstatusset1: Reg<PSTATUSSET_SPEC>0x125 - HOST End Point Pipe Status Set
pstatus1: Reg<PSTATUS_SPEC>0x126 - HOST End Point Pipe Status
pintflag1: Reg<PINTFLAG_SPEC>0x127 - HOST Pipe Interrupt Flag
pintenclr1: Reg<PINTENCLR_SPEC>0x128 - HOST Pipe Interrupt Flag Clear
pintenset1: Reg<PINTENSET_SPEC>0x129 - HOST Pipe Interrupt Flag Set
pcfg2: Reg<PCFG_SPEC>0x140 - HOST End Point Configuration
binterval2: Reg<BINTERVAL_SPEC>0x143 - HOST Bus Access Period of Pipe
pstatusclr2: Reg<PSTATUSCLR_SPEC>0x144 - HOST End Point Pipe Status Clear
pstatusset2: Reg<PSTATUSSET_SPEC>0x145 - HOST End Point Pipe Status Set
pstatus2: Reg<PSTATUS_SPEC>0x146 - HOST End Point Pipe Status
pintflag2: Reg<PINTFLAG_SPEC>0x147 - HOST Pipe Interrupt Flag
pintenclr2: Reg<PINTENCLR_SPEC>0x148 - HOST Pipe Interrupt Flag Clear
pintenset2: Reg<PINTENSET_SPEC>0x149 - HOST Pipe Interrupt Flag Set
pcfg3: Reg<PCFG_SPEC>0x160 - HOST End Point Configuration
binterval3: Reg<BINTERVAL_SPEC>0x163 - HOST Bus Access Period of Pipe
pstatusclr3: Reg<PSTATUSCLR_SPEC>0x164 - HOST End Point Pipe Status Clear
pstatusset3: Reg<PSTATUSSET_SPEC>0x165 - HOST End Point Pipe Status Set
pstatus3: Reg<PSTATUS_SPEC>0x166 - HOST End Point Pipe Status
pintflag3: Reg<PINTFLAG_SPEC>0x167 - HOST Pipe Interrupt Flag
pintenclr3: Reg<PINTENCLR_SPEC>0x168 - HOST Pipe Interrupt Flag Clear
pintenset3: Reg<PINTENSET_SPEC>0x169 - HOST Pipe Interrupt Flag Set
pcfg4: Reg<PCFG_SPEC>0x180 - HOST End Point Configuration
binterval4: Reg<BINTERVAL_SPEC>0x183 - HOST Bus Access Period of Pipe
pstatusclr4: Reg<PSTATUSCLR_SPEC>0x184 - HOST End Point Pipe Status Clear
pstatusset4: Reg<PSTATUSSET_SPEC>0x185 - HOST End Point Pipe Status Set
pstatus4: Reg<PSTATUS_SPEC>0x186 - HOST End Point Pipe Status
pintflag4: Reg<PINTFLAG_SPEC>0x187 - HOST Pipe Interrupt Flag
pintenclr4: Reg<PINTENCLR_SPEC>0x188 - HOST Pipe Interrupt Flag Clear
pintenset4: Reg<PINTENSET_SPEC>0x189 - HOST Pipe Interrupt Flag Set
pcfg5: Reg<PCFG_SPEC>0x1a0 - HOST End Point Configuration
binterval5: Reg<BINTERVAL_SPEC>0x1a3 - HOST Bus Access Period of Pipe
pstatusclr5: Reg<PSTATUSCLR_SPEC>0x1a4 - HOST End Point Pipe Status Clear
pstatusset5: Reg<PSTATUSSET_SPEC>0x1a5 - HOST End Point Pipe Status Set
pstatus5: Reg<PSTATUS_SPEC>0x1a6 - HOST End Point Pipe Status
pintflag5: Reg<PINTFLAG_SPEC>0x1a7 - HOST Pipe Interrupt Flag
pintenclr5: Reg<PINTENCLR_SPEC>0x1a8 - HOST Pipe Interrupt Flag Clear
pintenset5: Reg<PINTENSET_SPEC>0x1a9 - HOST Pipe Interrupt Flag Set
pcfg6: Reg<PCFG_SPEC>0x1c0 - HOST End Point Configuration
binterval6: Reg<BINTERVAL_SPEC>0x1c3 - HOST Bus Access Period of Pipe
pstatusclr6: Reg<PSTATUSCLR_SPEC>0x1c4 - HOST End Point Pipe Status Clear
pstatusset6: Reg<PSTATUSSET_SPEC>0x1c5 - HOST End Point Pipe Status Set
pstatus6: Reg<PSTATUS_SPEC>0x1c6 - HOST End Point Pipe Status
pintflag6: Reg<PINTFLAG_SPEC>0x1c7 - HOST Pipe Interrupt Flag
pintenclr6: Reg<PINTENCLR_SPEC>0x1c8 - HOST Pipe Interrupt Flag Clear
pintenset6: Reg<PINTENSET_SPEC>0x1c9 - HOST Pipe Interrupt Flag Set
pcfg7: Reg<PCFG_SPEC>0x1e0 - HOST End Point Configuration
binterval7: Reg<BINTERVAL_SPEC>0x1e3 - HOST Bus Access Period of Pipe
pstatusclr7: Reg<PSTATUSCLR_SPEC>0x1e4 - HOST End Point Pipe Status Clear
pstatusset7: Reg<PSTATUSSET_SPEC>0x1e5 - HOST End Point Pipe Status Set
pstatus7: Reg<PSTATUS_SPEC>0x1e6 - HOST End Point Pipe Status
pintflag7: Reg<PINTFLAG_SPEC>0x1e7 - HOST Pipe Interrupt Flag
pintenclr7: Reg<PINTENCLR_SPEC>0x1e8 - HOST Pipe Interrupt Flag Clear
pintenset7: Reg<PINTENSET_SPEC>0x1e9 - HOST Pipe Interrupt Flag Set