Enum SafeClockDiv

#[repr(u8)]
pub enum SafeClockDiv {
    Div1 = 0,
    Div2 = 1,
    Div4 = 2,
    Div8 = 3,
    Div16 = 4,
    Div32 = 5,
    Div64 = 6,
    Div128 = 7,
    Div256 = 8,
    Div512 = 9,
    Div1024 = 10,
    Div2048 = 11,
    Div4096 = 12,
    Div8192 = 13,
    Div16384 = 14,
    Div32768 = 15,
}

Division factor for the safe clock prescaler

If an Xosc clock failure is detected, the hardware will switch to a safe clock derived from the Dfll. This enum sets the divider between the 48 MHz DFLL and the safe clock frequency. The divider can be any value of 2^N, with N in the range 0..16.

Variants

Div1 = 0

Div2 = 1

Div4 = 2

Div8 = 3

Div16 = 4

Div32 = 5

Div64 = 6

Div128 = 7

Div256 = 8

Div512 = 9

Div1024 = 10

Div2048 = 11

Div4096 = 12

Div8192 = 13

Div16384 = 14

Div32768 = 15

Trait Implementations

impl Clone for SafeClockDiv

fn clone(&self) -> SafeClockDiv

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for SafeClockDiv

fn default() -> SafeClockDiv

Returns the “default value” for a type.

impl PartialEq for SafeClockDiv

fn eq(&self, other: &SafeClockDiv) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for SafeClockDiv

impl Eq for SafeClockDiv

impl StructuralPartialEq for SafeClockDiv