Struct Nvm

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pub struct Nvm { /* private fields */ }

Expand description

Non-volatile memory controller

Implementations§

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impl Nvm

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pub const USERPAGE_ADDR: const [u8; 512] = {0x804000 as const [u8; 512]}

Pointer to the userpage region of the flash memory

Note: Never call core::ptr::read_volatile on this pointer, yields very poor codegen (around 9 KiB bytes of code)

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pub fn new(nvm: Nvmctrl) -> Self

Create a new NVM controller or handle failure from DSU

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pub unsafe fn registers(&self) -> &Nvmctrl

Raw access to the registers.

§Safety

The abstraction assumes that it has exclusive ownership of the registers. Direct access can break such assumptions.

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pub unsafe fn bank_swap(&mut self) -> !

Swap the flash banks. The processor will be reset, after which the inactive bank will become the active bank.

§Safety

Ensure there is a working, memory safe program in place in the inactive bank before calling.

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pub fn power_reduction_mode(&mut self, prm: Prmselect)

Set the power reduction mode

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pub fn is_boot_protected(&self) -> bool

Check if the flash is boot protected

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pub fn first_bank(&self) -> PhysicalBank

Get first bank

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pub fn read_userpage(&self) -> Userpage

Read the user page from the flash memory

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pub unsafe fn modify_userpage( &mut self, f: impl FnOnce(&mut Userpage), ) -> Result<UserpageStatus>

Modify the NVM User Page (aka User Row/UROW)

User is expected to provide a closure that modifies the user page according to the user’s needs.

This method will read the current user page, call the closure on it, erase the page in the flash memory and write it back again.

Erasure and flashing is skipped if the userpage stays the same after calling the closure on it.

§Safety

Even though factory calibration settings are not modifiable via setters they can be still mutated via raw access to the userpage.0 field.

Power loss between the erase and the write will result in data loss.

Thus, users are advised to backup factory calibration settings before mutating the user page!

If these settings are erased, device might stop behaving correctly!

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pub fn calibration_area(&self) -> CalibrationArea

Read the calibration area

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pub fn temperatures_calibration_area(&self) -> TemperaturesCalibrationArea

Read the calibration area for temperatures

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pub fn enable_security_bit(&mut self) -> Result<()>

Enable security bit

It locks the chip from external access for code security. Consult the datasheet for more details.

In order to disable it, chip erase command must be issued through the debugger.

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pub unsafe fn enable_chip_erase_lock(&mut self) -> Result<()>

Enable the chip erase lock

It disables the chip erase capability.

§Safety

Together with Self::enable_security_bit, it completely locks the MCU down from any external interaction via debugger, thus effectively bricking the device. Flashed firmware must provide a way to execute Self::disable_chip_erase_lock method in order to enable the debugger access again.

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pub fn disable_chip_erase_lock(&mut self) -> Result<()>

Disable the chip erase lock

It enables the chip erase capability through the debugger.

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pub fn boot_protection(&mut self, protect: bool) -> Result<()>

Enable/disable boot protection

Userpage’s NVM BOOT field defines a memory region that is supposed to be protected. Nvmctrl.STATUS.BOOTPROT is a readonly HW register populated on reset with a value from a userpage. By default, 0

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pub fn region_lock(&mut self, mask: u32) -> Result<()>

Enable/disable region lock

Flash memory is split into 32 regions. The 32 bits of the mask determine if each region should be locked (if its bit is 0) and prevent writing and erasing pages, or unlocked (if its bit is 1) and allow writing and erasing pages.

Less significant bits represent lower addresses, more significant bits represent higher addresses.

For example mask 0xFFFF_0000 implies that active bank should be locked while inactive bank should be unlocked.

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