Enum TriggerSource

#[repr(u8)]
pub enum TriggerSource {
    Disable = 0,
    RtcTimestamp = 1,
    DsuDcc0 = 2,
    DsuDcc1 = 3,
    Sercom0Rx = 4,
    Sercom0Tx = 5,
    Sercom1Rx = 6,
    Sercom1Tx = 7,
    Sercom2Rx = 8,
    Sercom2Tx = 9,
    Sercom3Rx = 10,
    Sercom3Tx = 11,
    Sercom4Rx = 12,
    Sercom4Tx = 13,
    Sercom5Rx = 14,
    Sercom5Tx = 15,
    Sercom6Rx = 16,
    Sercom6Tx = 17,
    Sercom7Rx = 18,
    Sercom7Tx = 19,
    Can0Debug = 20,
    Can1Debug = 21,
    Tcc0Ovf = 22,
    Tcc0Mc0 = 23,
    Tcc0Mc1 = 24,
    Tcc0Mc2 = 25,
    Tcc0Mc3 = 26,
    Tcc0Mc4 = 27,
    Tcc0Mc5 = 28,
    Tcc1Ovf = 29,
    Tcc1Mc0 = 30,
    Tcc1Mc1 = 31,
    Tcc1Mc2 = 32,
    Tcc1Mc3 = 33,
    Tcc2Ovf = 34,
    Tcc2Mc0 = 35,
    Tcc2Mc1 = 36,
    Tcc2Mc2 = 37,
    Tcc3Ovf = 38,
    Tcc3Mc0 = 39,
    Tcc3Mc1 = 40,
    Tcc4Ovf = 41,
    Tcc4Mc0 = 42,
    Tcc4Mc1 = 43,
    Tc0Ovf = 44,
    Tc0Mc0 = 45,
    Tc0Mc1 = 46,
    Tc1Ovf = 47,
    Tc1Mc0 = 48,
    Tc1Mc1 = 49,
    Tc2Ovf = 50,
    Tc2Mc0 = 51,
    Tc2Mc1 = 52,
    Tc3Ovf = 53,
    Tc3Mc0 = 54,
    Tc3Mc1 = 55,
    Tc4Ovf = 56,
    Tc4Mc0 = 57,
    Tc4Mc1 = 58,
    Tc5Ovf = 59,
    Tc5Mc0 = 60,
    Tc5Mc1 = 61,
    Tc6Ovf = 62,
    Tc6Mc0 = 63,
    Tc6Mc1 = 64,
    Tc7Ovf = 65,
    Tc7Mc0 = 66,
    Tc7Mc1 = 67,
    Adc0Resrdy = 68,
    Adc0Seq = 69,
    Adc1Resrdy = 70,
    Adc1Seq = 71,
    DacEmpty0 = 72,
    DacEmpty1 = 73,
    DacResrdy0 = 74,
    DacResrdy1 = 75,
    I2sRx0 = 76,
    I2sRx1 = 77,
    I2sTx0 = 78,
    I2sTx1 = 79,
    PccRx = 80,
    AesWr = 81,
    AesRd = 82,
    QspiRx = 83,
    QspiTx = 84,
}

Trigger Source

Value on reset: 0

Variants

Disable = 0

0: Only software/event triggers

RtcTimestamp = 1

1: DMA RTC timestamp trigger

DsuDcc0 = 2

2: DMAC ID for DCC0 register

DsuDcc1 = 3

3: DMAC ID for DCC1 register

Sercom0Rx = 4

4: Index of DMA RX trigger

Sercom0Tx = 5

5: Index of DMA TX trigger

Sercom1Rx = 6

6: Index of DMA RX trigger

Sercom1Tx = 7

7: Index of DMA TX trigger

Sercom2Rx = 8

8: Index of DMA RX trigger

Sercom2Tx = 9

9: Index of DMA TX trigger

Sercom3Rx = 10

10: Index of DMA RX trigger

Sercom3Tx = 11

11: Index of DMA TX trigger

Sercom4Rx = 12

12: Index of DMA RX trigger

Sercom4Tx = 13

13: Index of DMA TX trigger

Sercom5Rx = 14

14: Index of DMA RX trigger

Sercom5Tx = 15

15: Index of DMA TX trigger

Sercom6Rx = 16

16: Index of DMA RX trigger

Sercom6Tx = 17

17: Index of DMA TX trigger

Sercom7Rx = 18

18: Index of DMA RX trigger

Sercom7Tx = 19

19: Index of DMA TX trigger

Can0Debug = 20

20: DMA CAN Debug Req

Can1Debug = 21

21: DMA CAN Debug Req

Tcc0Ovf = 22

22: DMA overflow/underflow/retrigger trigger

Tcc0Mc0 = 23

23: Indexes of DMA Match/Compare triggers

Tcc0Mc1 = 24

24: Indexes of DMA Match/Compare triggers

Tcc0Mc2 = 25

25: Indexes of DMA Match/Compare triggers

Tcc0Mc3 = 26

26: Indexes of DMA Match/Compare triggers

Tcc0Mc4 = 27

27: Indexes of DMA Match/Compare triggers

Tcc0Mc5 = 28

28: Indexes of DMA Match/Compare triggers

Tcc1Ovf = 29

29: DMA overflow/underflow/retrigger trigger

Tcc1Mc0 = 30

30: Indexes of DMA Match/Compare triggers

Tcc1Mc1 = 31

31: Indexes of DMA Match/Compare triggers

Tcc1Mc2 = 32

32: Indexes of DMA Match/Compare triggers

Tcc1Mc3 = 33

33: Indexes of DMA Match/Compare triggers

Tcc2Ovf = 34

34: DMA overflow/underflow/retrigger trigger

Tcc2Mc0 = 35

35: Indexes of DMA Match/Compare triggers

Tcc2Mc1 = 36

36: Indexes of DMA Match/Compare triggers

Tcc2Mc2 = 37

37: Indexes of DMA Match/Compare triggers

Tcc3Ovf = 38

38: DMA overflow/underflow/retrigger trigger

Tcc3Mc0 = 39

39: Indexes of DMA Match/Compare triggers

Tcc3Mc1 = 40

40: Indexes of DMA Match/Compare triggers

Tcc4Ovf = 41

41: DMA overflow/underflow/retrigger trigger

Tcc4Mc0 = 42

42: Indexes of DMA Match/Compare triggers

Tcc4Mc1 = 43

43: Indexes of DMA Match/Compare triggers

Tc0Ovf = 44

44: Indexes of DMA Overflow trigger

Tc0Mc0 = 45

45: Indexes of DMA Match/Compare triggers

Tc0Mc1 = 46

46: Indexes of DMA Match/Compare triggers

Tc1Ovf = 47

47: Indexes of DMA Overflow trigger

Tc1Mc0 = 48

48: Indexes of DMA Match/Compare triggers

Tc1Mc1 = 49

49: Indexes of DMA Match/Compare triggers

Tc2Ovf = 50

50: Indexes of DMA Overflow trigger

Tc2Mc0 = 51

51: Indexes of DMA Match/Compare triggers

Tc2Mc1 = 52

52: Indexes of DMA Match/Compare triggers

Tc3Ovf = 53

53: Indexes of DMA Overflow trigger

Tc3Mc0 = 54

54: Indexes of DMA Match/Compare triggers

Tc3Mc1 = 55

55: Indexes of DMA Match/Compare triggers

Tc4Ovf = 56

56: Indexes of DMA Overflow trigger

Tc4Mc0 = 57

57: Indexes of DMA Match/Compare triggers

Tc4Mc1 = 58

58: Indexes of DMA Match/Compare triggers

Tc5Ovf = 59

59: Indexes of DMA Overflow trigger

Tc5Mc0 = 60

60: Indexes of DMA Match/Compare triggers

Tc5Mc1 = 61

61: Indexes of DMA Match/Compare triggers

Tc6Ovf = 62

62: Indexes of DMA Overflow trigger

Tc6Mc0 = 63

63: Indexes of DMA Match/Compare triggers

Tc6Mc1 = 64

64: Indexes of DMA Match/Compare triggers

Tc7Ovf = 65

65: Indexes of DMA Overflow trigger

Tc7Mc0 = 66

66: Indexes of DMA Match/Compare triggers

Tc7Mc1 = 67

67: Indexes of DMA Match/Compare triggers

Adc0Resrdy = 68

68: index of DMA RESRDY trigger

Adc0Seq = 69

69: Index of DMA SEQ trigger

Adc1Resrdy = 70

70: Index of DMA RESRDY trigger

Adc1Seq = 71

71: Index of DMA SEQ trigger

DacEmpty0 = 72

72: DMA DAC Empty Req

DacEmpty1 = 73

73: DMA DAC Empty Req

DacResrdy0 = 74

74: DMA DAC Result Ready Req

DacResrdy1 = 75

75: DMA DAC Result Ready Req

I2sRx0 = 76

76: Indexes of DMA RX triggers

I2sRx1 = 77

77: Indexes of DMA RX triggers

I2sTx0 = 78

78: Indexes of DMA TX triggers

I2sTx1 = 79

79: Indexes of DMA TX triggers

PccRx = 80

80: Indexes of PCC RX trigger

AesWr = 81

81: DMA DATA Write trigger

AesRd = 82

82: DMA DATA Read trigger

QspiRx = 83

83: Indexes of QSPI RX trigger

QspiTx = 84

84: Indexes of QSPI TX trigger

Trait Implementations

impl Clone for Trigsrcselect

fn clone(&self) -> Trigsrcselect

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Trigsrcselect

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl FieldSpec for Trigsrcselect

type Ux = u8

Raw field type (u8, u16, u32, …).

impl PartialEq for Trigsrcselect

fn eq(&self, other: &Trigsrcselect) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Trigsrcselect

impl Eq for Trigsrcselect

impl IsEnum for Trigsrcselect

impl StructuralPartialEq for Trigsrcselect