pub struct Spi<C, A, RxDma = NoneT, TxDma = NoneT>where
C: ValidConfig,
A: Capability,{ /* private fields */ }Expand description
An enabled SPI peripheral that can perform transactions
See the impl_ehal documentation for details on the implementations of
the embedded HAL traits, which vary based on Size and Capability.
Implementations§
Source§impl<C, A, S> Spi<C, A>
impl<C, A, S> Spi<C, A>
Sourcepub fn into_future<I>(self, _interrupts: I) -> SpiFuture<C, A>
pub fn into_future<I>(self, _interrupts: I) -> SpiFuture<C, A>
In cases where the underlying Spi is Duplex, reading words need
to be accompanied with sending a no-op word. By default it is set to
0x00, but you can configure it using Config::set_nop_word.
Source§impl<C, A, RxDma, TxDma> Spi<C, A, RxDma, TxDma>where
C: ValidConfig,
A: Capability,
impl<C, A, RxDma, TxDma> Spi<C, A, RxDma, TxDma>where
C: ValidConfig,
A: Capability,
Sourcepub fn reconfigure(&mut self, update: impl FnOnce(&mut SpecificConfig<C>))
pub fn reconfigure(&mut self, update: impl FnOnce(&mut SpecificConfig<C>))
Update the SPI configuration.
Calling this method will temporarily disable the SERCOM peripheral, as some registers are enable-protected. This may interrupt any ongoing transactions.
Sourcepub fn enable_interrupts(&mut self, flags: Flags)
pub fn enable_interrupts(&mut self, flags: Flags)
Enable interrupts for the specified flags
Sourcepub fn disable_interrupts(&mut self, flags: Flags)
pub fn disable_interrupts(&mut self, flags: Flags)
Disable interrupts for the specified flags
Sourcepub fn read_flags(&self) -> Flags
pub fn read_flags(&self) -> Flags
Read the interrupt flags
Sourcepub fn clear_flags(&mut self, flags: Flags)
pub fn clear_flags(&mut self, flags: Flags)
Clear the corresponding interrupt flags
Only the ERROR, SSL and TXC flags can be cleared.
Note: Implementations of flush methods (eg SpiBus::flush) wait
on and clear the TXC flag. Manually clearing this flag could cause
them to hang indefinitely.
Sourcepub fn read_status(&self) -> Status
pub fn read_status(&self) -> Status
Read the error status flags
Sourcepub fn clear_status(&mut self, status: Status)
pub fn clear_status(&mut self, status: Status)
Clear the corresponding error status flags
Sourcepub fn read_flags_errors(&self) -> Result<Flags, Error>
pub fn read_flags_errors(&self) -> Result<Flags, Error>
Try to read the interrupt flags, but first check the error status flags.
Sourcepub unsafe fn read_data(&mut self) -> DataWidth
pub unsafe fn read_data(&mut self) -> DataWidth
Read from the DATA register
§Safety
Reading from the data register directly is unsafe, because it will
clear the RXC flag, which could break assumptions made elsewhere in
this module.
Sourcepub unsafe fn write_data(&mut self, data: DataWidth)
pub unsafe fn write_data(&mut self, data: DataWidth)
Write to the DATA register
§Safety
Writing to the data register directly is unsafe, because it will clear
the DRE flag, which could break assumptions made elsewhere in this
module.
Source§impl<C, D> Spi<C, D>
impl<C, D> Spi<C, D>
Sourcepub fn with_dma_channels<R, T>(self, rx: R, tx: T) -> Spi<C, D, R, T>
pub fn with_dma_channels<R, T>(self, rx: R, tx: T) -> Spi<C, D, R, T>
Source§impl<C> Spi<C, Duplex>where
C: ValidConfig<OpMode = Slave>,
impl<C> Spi<C, Duplex>where
C: ValidConfig<OpMode = Slave>,
Sourcepub fn with_dma_channels_slave<R, T>(self, rx: R, tx: T) -> Spi<C, Duplex, R, T>
pub fn with_dma_channels_slave<R, T>(self, rx: R, tx: T) -> Spi<C, Duplex, R, T>
Source§impl<C, T> Spi<C, Rx, NoneT, T>where
C: ValidConfig<OpMode = Slave>,
impl<C, T> Spi<C, Rx, NoneT, T>where
C: ValidConfig<OpMode = Slave>,
Sourcepub fn with_rx_channel<R>(self, rx: R) -> Spi<C, Rx, R, T>where
R: AnyChannel<Status = Ready>,
pub fn with_rx_channel<R>(self, rx: R) -> Spi<C, Rx, R, T>where
R: AnyChannel<Status = Ready>,
Source§impl<C, R> Spi<C, Tx, R, NoneT>where
C: ValidConfig,
impl<C, R> Spi<C, Tx, R, NoneT>where
C: ValidConfig,
Sourcepub fn with_tx_channel<T>(self, tx: T) -> Spi<C, Tx, R, T>where
T: AnyChannel<Status = Ready>,
pub fn with_tx_channel<T>(self, tx: T) -> Spi<C, Tx, R, T>where
T: AnyChannel<Status = Ready>,
Source§impl<C, D, R, T> Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
impl<C, D, R, T> Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
Sourcepub fn take_dma_channels(self) -> (Spi<C, D, NoneT, NoneT>, R, T)
pub fn take_dma_channels(self) -> (Spi<C, D, NoneT, NoneT>, R, T)
Reclaim both RX and TX DMA channels. Any subsequent SPI transaction will not use DMA.
Sourcepub fn take_rx_channel(self) -> (Spi<C, D, NoneT, T>, R)where
R: AnyChannel<Status: ReadyChannel>,
pub fn take_rx_channel(self) -> (Spi<C, D, NoneT, T>, R)where
R: AnyChannel<Status: ReadyChannel>,
Reclaim the RX DMA channel. Any subsequent SPI RX transaction will not use DMA.
Sourcepub fn take_tx_channel(self) -> (Spi<C, D, R, NoneT>, T)where
T: AnyChannel<Status: ReadyChannel>,
pub fn take_tx_channel(self) -> (Spi<C, D, R, NoneT>, T)where
T: AnyChannel<Status: ReadyChannel>,
Reclaim the TX DMA channel. Any subsequent SPI TX transaction will not use DMA.
Source§impl<C: ValidConfig, R, T> Spi<C, Tx, R, T>
impl<C: ValidConfig, R, T> Spi<C, Tx, R, T>
Sourcepub fn into_panic_on_write(self) -> PanicOnWrite<Self>
pub fn into_panic_on_write(self) -> PanicOnWrite<Self>
Turn a Tx Spi into a PanicOnWrite
Source§impl<C: ValidConfig, R, T> Spi<C, Tx, R, T>
impl<C: ValidConfig, R, T> Spi<C, Tx, R, T>
Sourcepub fn into_panic_on_read(self) -> PanicOnRead<Self>
pub fn into_panic_on_read(self) -> PanicOnRead<Self>
Turn a Rx Spi into a PanicOnRead
Source§impl<P, M, A> Spi<Config<P, M, DynLength>, A>
impl<P, M, A> Spi<Config<P, M, DynLength>, A>
Sourcepub fn get_dyn_length(&self) -> u8
pub fn get_dyn_length(&self) -> u8
Return the current transaction length
Read the LENGTH register to determine the current transaction length
Sourcepub fn set_dyn_length(&mut self, length: u8)
pub fn set_dyn_length(&mut self, length: u8)
Set the transaction length
Write the LENGTH register to set the transaction length. Panics if the length is zero.
Changing the transaction LENGTH while is enabled is permissible but
dangerous. If you have sent or received any bytes at the current
LENGTH, you must wait for a TXC flag before changing to a new
LENGTH.
Trait Implementations§
Source§impl<C, A> AnySpi for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AnySpi for Spi<C, A>where
C: ValidConfig,
A: Capability,
Source§impl<C, A> AsMut<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AsMut<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
Source§impl<C, A, R, T> AsMut<Spi<C, A, R, T>> for SpiFuture<C, A, R, T>where
C: ValidConfig,
A: Capability,
impl<C, A, R, T> AsMut<Spi<C, A, R, T>> for SpiFuture<C, A, R, T>where
C: ValidConfig,
A: Capability,
Source§impl<C: ValidConfig, R, T> AsMut<Spi<C, Rx, R, T>> for PanicOnWrite<Spi<C, Rx, R, T>>
impl<C: ValidConfig, R, T> AsMut<Spi<C, Rx, R, T>> for PanicOnWrite<Spi<C, Rx, R, T>>
Source§impl<C: ValidConfig, R, T> AsMut<Spi<C, Tx, R, T>> for PanicOnRead<Spi<C, Tx, R, T>>
impl<C: ValidConfig, R, T> AsMut<Spi<C, Tx, R, T>> for PanicOnRead<Spi<C, Tx, R, T>>
Source§impl<C, A> AsRef<Config<<C as AnyConfig>::Pads, <C as AnyConfig>::OpMode, <C as AnyConfig>::Size>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
Get a shared reference to the underlying Config struct
impl<C, A> AsRef<Config<<C as AnyConfig>::Pads, <C as AnyConfig>::OpMode, <C as AnyConfig>::Size>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
Get a shared reference to the underlying Config struct
This can be used to call the various get_* functions on Config
Source§fn as_ref(&self) -> &SpecificConfig<C>
fn as_ref(&self) -> &SpecificConfig<C>
Source§impl<C, A> AsRef<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
impl<C, A> AsRef<Spi<C, A>> for Spi<C, A>where
C: ValidConfig,
A: Capability,
Source§impl<C, A, R, T> AsRef<Spi<C, A, R, T>> for SpiFuture<C, A, R, T>where
C: ValidConfig,
A: Capability,
impl<C, A, R, T> AsRef<Spi<C, A, R, T>> for SpiFuture<C, A, R, T>where
C: ValidConfig,
A: Capability,
Source§impl<C: ValidConfig, R, T> AsRef<Spi<C, Rx, R, T>> for PanicOnWrite<Spi<C, Rx, R, T>>
impl<C: ValidConfig, R, T> AsRef<Spi<C, Rx, R, T>> for PanicOnWrite<Spi<C, Rx, R, T>>
Source§impl<C: ValidConfig, R, T> AsRef<Spi<C, Tx, R, T>> for PanicOnRead<Spi<C, Tx, R, T>>
impl<C: ValidConfig, R, T> AsRef<Spi<C, Tx, R, T>> for PanicOnRead<Spi<C, Tx, R, T>>
Source§impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
Source§impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
Source§impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
impl<C, D, R, T> ErrorType for Spi<C, D, R, T>where
C: ValidConfig,
D: Capability,
Source§impl<C: ValidConfig, R, T> From<PanicOnRead<Spi<C, Tx, R, T>>> for Spi<C, Tx, R, T>
impl<C: ValidConfig, R, T> From<PanicOnRead<Spi<C, Tx, R, T>>> for Spi<C, Tx, R, T>
Source§impl<C: ValidConfig, R, T> From<PanicOnWrite<Spi<C, Rx, R, T>>> for Spi<C, Rx, R, T>
impl<C: ValidConfig, R, T> From<PanicOnWrite<Spi<C, Rx, R, T>>> for Spi<C, Rx, R, T>
Source§impl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<DataWidth>,
DataWidth: AsPrimitive<C::Word>,
impl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<DataWidth>,
DataWidth: AsPrimitive<C::Word>,
Source§impl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement ehal_nb::serial::Read for Rx Spi structs in a
MasterMode
impl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement ehal_nb::serial::Read for Rx Spi structs in a
MasterMode
serial::Read is only implemented for Spi structs with Rx
Capability. In a MasterMode, Read has to initiate transactions, so
it keeps track of the transaction state. If a transaction is in progress, it
will wait on RXC. If not, it will wait on DRE, and then send 0.
Source§impl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement serial::Read for Rx Spi structs in Slave
OpMode
impl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement serial::Read for Rx Spi structs in Slave
OpMode
serial::Read is only implemented for Spi structs with Rx
Capability. In Slave OpMode, Read does not have to initiate
transactions, so it does not have to store any internal state. It only has
to wait on RXC.
Source§impl<P, M, Z, D, R, T, S> Read for Spi<Config<P, M, Z>, D, R, T>where
P: ValidPads,
M: MasterMode,
Z: Size<Word = u8> + 'static,
Config<P, M, Z>: ValidConfig<Sercom = S>,
D: Receive,
S: Sercom,
R: AnyChannel<Status = Ready>,
T: AnyChannel<Status = Ready>,
embedded_io::Read implementation for Receive Spis in
MasterMode, using DMA transfers.
impl<P, M, Z, D, R, T, S> Read for Spi<Config<P, M, Z>, D, R, T>where
P: ValidPads,
M: MasterMode,
Z: Size<Word = u8> + 'static,
Config<P, M, Z>: ValidConfig<Sercom = S>,
D: Receive,
S: Sercom,
R: AnyChannel<Status = Ready>,
T: AnyChannel<Status = Ready>,
embedded_io::Read implementation for Receive Spis in
MasterMode, using DMA transfers.
Source§fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>
Source§fn read_exact(
&mut self,
buf: &mut [u8],
) -> Result<(), ReadExactError<Self::Error>>
fn read_exact( &mut self, buf: &mut [u8], ) -> Result<(), ReadExactError<Self::Error>>
buf. Read moreSource§impl<P, Z, D, R, T, S> Read for Spi<Config<P, Slave, Z>, D, R, T>where
P: ValidPads,
Z: Size<Word = u8> + 'static,
Config<P, Slave, Z>: ValidConfig<Sercom = S>,
D: Receive,
S: Sercom,
R: AnyChannel<Status = Ready>,
embedded_io::Read implementation for Receive Spis in Slave
mode, using DMA transfers.
impl<P, Z, D, R, T, S> Read for Spi<Config<P, Slave, Z>, D, R, T>where
P: ValidPads,
Z: Size<Word = u8> + 'static,
Config<P, Slave, Z>: ValidConfig<Sercom = S>,
D: Receive,
S: Sercom,
R: AnyChannel<Status = Ready>,
embedded_io::Read implementation for Receive Spis in Slave
mode, using DMA transfers.
Source§fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error>
Source§fn read_exact(
&mut self,
buf: &mut [u8],
) -> Result<(), ReadExactError<Self::Error>>
fn read_exact( &mut self, buf: &mut [u8], ) -> Result<(), ReadExactError<Self::Error>>
buf. Read moreSource§impl<P, M, C> SpiBus<<C as Length>::Word> for Spi<Config<P, M, C>, Duplex>where
Config<P, M, C>: ValidConfig,
P: ValidPads,
M: MasterMode,
C: Size + 'static,
C::Word: PrimInt + AsPrimitive<DataWidth> + Copy,
DataWidth: AsPrimitive<C::Word>,
impl<P, M, C> SpiBus<<C as Length>::Word> for Spi<Config<P, M, C>, Duplex>where
Config<P, M, C>: ValidConfig,
P: ValidPads,
M: MasterMode,
C: Size + 'static,
C::Word: PrimInt + AsPrimitive<DataWidth> + Copy,
DataWidth: AsPrimitive<C::Word>,
Source§fn read(&mut self, words: &mut [Word<C>]) -> Result<(), Self::Error>
fn read(&mut self, words: &mut [Word<C>]) -> Result<(), Self::Error>
words from the slave. Read moreSource§fn write(&mut self, words: &[Word<C>]) -> Result<(), Self::Error>
fn write(&mut self, words: &[Word<C>]) -> Result<(), Self::Error>
words to the slave, ignoring all the incoming words. Read moreSource§fn transfer(
&mut self,
read: &mut [Word<C>],
write: &[Word<C>],
) -> Result<(), Self::Error>
fn transfer( &mut self, read: &mut [Word<C>], write: &[Word<C>], ) -> Result<(), Self::Error>
write is written to the slave on MOSI and
words received on MISO are stored in read. Read moreSource§impl<P, M, S, C, R, T> SpiBus<<C as Length>::Word> for Spi<Config<P, M, C>, Duplex, R, T>where
Config<P, M, C>: ValidConfig<Sercom = S>,
S: Sercom,
P: ValidPads,
M: MasterMode,
C: Size + 'static,
C::Word: PrimInt + AsPrimitive<DataWidth> + Beat,
DataWidth: AsPrimitive<C::Word>,
R: AnyChannel<Status = Ready>,
T: AnyChannel<Status = Ready>,
impl<P, M, S, C, R, T> SpiBus<<C as Length>::Word> for Spi<Config<P, M, C>, Duplex, R, T>where
Config<P, M, C>: ValidConfig<Sercom = S>,
S: Sercom,
P: ValidPads,
M: MasterMode,
C: Size + 'static,
C::Word: PrimInt + AsPrimitive<DataWidth> + Beat,
DataWidth: AsPrimitive<C::Word>,
R: AnyChannel<Status = Ready>,
T: AnyChannel<Status = Ready>,
Source§fn read(&mut self, words: &mut [C::Word]) -> Result<(), Self::Error>
fn read(&mut self, words: &mut [C::Word]) -> Result<(), Self::Error>
words from the slave. Read moreSource§fn write(&mut self, words: &[C::Word]) -> Result<(), Self::Error>
fn write(&mut self, words: &[C::Word]) -> Result<(), Self::Error>
words to the slave, ignoring all the incoming words. Read moreSource§fn transfer(
&mut self,
read: &mut [C::Word],
write: &[C::Word],
) -> Result<(), Self::Error>
fn transfer( &mut self, read: &mut [C::Word], write: &[C::Word], ) -> Result<(), Self::Error>
write is written to the slave on MOSI and
words received on MISO are stored in read. Read moreSource§impl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>
Implement ehal_nb::serial::Write for Tx Spi structs
impl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>
Implement ehal_nb::serial::Write for Tx Spi structs
serial::Write is only implemented for Spi structs with Tx
Capability. Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M, Z, D, R, T, S> Write for Spi<Config<P, M, Z>, D, R, T>where
P: ValidPads,
M: OpMode,
Z: Size<Word = u8> + 'static,
Config<P, M, Z>: ValidConfig<Sercom = S>,
D: Transmit,
S: Sercom,
T: AnyChannel<Status = Ready>,
embedded_io::Write implementation for Transmit Spis in either
Slave or MasterMode, using DMA transfers.
impl<P, M, Z, D, R, T, S> Write for Spi<Config<P, M, Z>, D, R, T>where
P: ValidPads,
M: OpMode,
Z: Size<Word = u8> + 'static,
Config<P, M, Z>: ValidConfig<Sercom = S>,
D: Transmit,
S: Sercom,
T: AnyChannel<Status = Ready>,
embedded_io::Write implementation for Transmit Spis in either
Slave or MasterMode, using DMA transfers.
Source§fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error>
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error>
Source§fn flush(&mut self) -> Result<(), Self::Error>
fn flush(&mut self) -> Result<(), Self::Error>
Source§impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
impl<P, M> WriteIter<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>
Implement embedded-hal 0.2 WriteIter for Spi structs
with Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M, A> Transfer<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
impl<P, M, A> Transfer<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
The transaction Length must be <= 4. The transfer accepts
a slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
The transaction Length must be <= 4. The transfer accepts
a slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
impl<P, M, A> Transfer<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
The transaction Length must be <= 4. The transfer accepts
a slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M, A> Transfer<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
impl<P, M, A> Transfer<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, A>
Implement embedded_hal 0.2 Transfer for Spi structs that
can Receive and have an AtomicSize
The transaction Length must be <= 4. The transfer accepts
a slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M, L, A> Transfer<u8> for Spi<Config<P, M, L>, A>
impl<P, M, L, A> Transfer<u8> for Spi<Config<P, M, L>, A>
Source§impl<P, M, A> Transfer<u8> for Spi<Config<P, M, DynLength>, A>
impl<P, M, A> Transfer<u8> for Spi<Config<P, M, DynLength>, A>
The transfer accepts a slice of u8 with a length equal to the run-time
dynamic transaction length. If the slice length does not match the result of
Spi::get_dyn_length, it will panic.
Source§impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UInt<UTerm, B1>, B0>, B0> as Length>::Word> for Spi<Config<P, M, U4>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B0> as Length>::Word> for Spi<Config<P, M, U2>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
impl<P, M> Write<<UInt<UInt<UTerm, B1>, B1> as Length>::Word> for Spi<Config<P, M, U3>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with
Duplex Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Source§impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
impl<P, M> Write<<UInt<UTerm, B1> as Length>::Word> for Spi<Config<P, M, U1>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with
Tx Capability and an AtomicSize
The transaction Length must be <= 4. The transfer accepts a
slice of primitive integers, depending on the Length (u8,
u16 or u32).
Because the Capability is Tx, this implementation never
reads the DATA register and ignores all buffer overflow errors.
Source§impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with Duplex
Capability and long transaction Lengths
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with Duplex
Capability and long transaction Lengths
Source§impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with Tx
Capability and long transaction Lengths
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with Tx
Capability and long transaction Lengths
Source§impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with Duplex
Capability and DynLength
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Duplex>
Implement embedded-hal 0.2 Write for Spi structs with Duplex
Capability and DynLength
The transfer accepts a [u8] with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length, it will panic.
Source§impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with Tx
Capability and DynLength
impl<P, M> Write<u8> for Spi<Config<P, M, DynLength>, Tx>
Implement embedded-hal 0.2 Write for Spi structs with Tx
Capability and DynLength
The transfer accepts a [u8] with a length equal to the run-time dynamic
transaction length. If the slice length does not match the result of
Spi::get_dyn_length], it will panic.
Because the Capability is Tx, this implementation never reads the DATA
register and ignores all buffer overflow errors.
Source§impl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement embedded-hal 0.2 serial::Read for Rx Spi structs in a
MasterMode
impl<P, M, L> Read<<L as Length>::Word> for Spi<Config<P, M, L>, Rx>where
Config<P, M, L>: ValidConfig,
P: ValidPads,
M: MasterMode,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement embedded-hal 0.2 serial::Read for Rx Spi structs in a
MasterMode
Refer to the serial::Read implementation of Spi for more details.
Source§impl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement embedded-hal 0.2 serial::Read for Rx Spi structs in
Slave OpMode
impl<P, L> Read<<L as Length>::Word> for Spi<Config<P, Slave, L>, Rx>where
Config<P, Slave, L>: ValidConfig,
P: ValidPads,
L: Length,
L::Word: PrimInt,
DataWidth: AsPrimitive<L::Word>,
Implement embedded-hal 0.2 serial::Read for Rx Spi structs in
Slave OpMode
Refer to the serial::Read implementation of Spi for more details.
Source§impl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>
Implement embedded-hal 0.2 serial::Write for Tx Spi structs
impl<C> Write<<C as AnyConfig>::Word> for Spi<C, Tx>
Implement embedded-hal 0.2 serial::Write for Tx Spi structs
Source§impl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<DataWidth>,
DataWidth: AsPrimitive<C::Word>,
Implement embedded-hal 0.2 spi::FullDuplex for Spi structs with AtomicSize
impl<C> FullDuplex<<C as AnyConfig>::Word> for Spi<C, Duplex>where
C: ValidConfig,
C::Size: AtomicSize,
C::Word: PrimInt + AsPrimitive<DataWidth>,
DataWidth: AsPrimitive<C::Word>,
Implement embedded-hal 0.2 spi::FullDuplex for Spi structs with AtomicSize