Struct Icm

pub struct Icm { /* private fields */ }

ICM Peripheral

Encapsulates the PAC which acts as a token and provides an interface to the ICM hardware

Implementations

impl Icm

pub fn new(icm: Icm) -> Self

Create the interface for the ICM peripheral

Don’t forget to enable the APB bus for ICM

AHB bus is on by default at reset

Clock::v1 mclk.apbcmask.modify(|_, w| w.icm_().set_bit());

Clock::v2 tokens.apbs.icm.enable();

pub fn enable(&mut self)

Enable the ICM peripheral

pub fn icm_status(&self) -> bool

Get enabled status of the ICM peripheral

pub fn disable(&mut self)

Disable the ICM peripheral

pub fn swrst(&mut self)

Reset the ICM controller

Does not seem to clear DSCR, HASH addr

The only way to clear the URAD and URAT fields is by resetting the ICM controller

pub fn destroy(self) -> Icm

Destroy the ICM peripheral and return the underlying ICM register

pub fn enable_region<N: RegionNum>(&mut self) -> Region<N>

pub fn enable_region0(&mut self) -> Region<Region0>

Enable region0

Creates an Region which provides region specific settings

pub fn enable_region1(&mut self) -> Region<Region1>

Enable region1

Creates an Region which provides region specific settings

pub fn enable_region2(&mut self) -> Region<Region2>

Enable region2

Creates an Region which provides region specific settings

pub fn enable_region3(&mut self) -> Region<Region3>

Enable region3

Creates an Region which provides region specific settings

pub fn set_hash_addr(&mut self, hash_addr_pointer: &HashArea)

Helper for setting the HASH addr

Expects a raw pointer to the memory address of the beginning of the designated variable but expressed as a multiple of 128

pub fn set_dscr_addr(&self, icm_region_desc: &MainRegionDesc<Region0>)

Set the DSCR addr to a specific MainRegionDesc

HW expects a raw pointer to the memory address of the beginning of the MainRegionDesc but expressed as a multiple of 64

pub fn set_user_initial_hash_value(&self, user_initial_hash_value: [u32; 8])

Set the user initial hash value

pub fn set_user_algorithm(self, algo: icm_algorithm)

Set the user hashing algorithm

pub fn set_user_configurable_hash(&self, user_configurable_hash: bool)

Activate user hash mode

Allows providing

• hash initial value
• Hash algorithm

Disables the ALGO field in MainRegionDesc

Set initial hash value via Icm::set_user_initial_hash_value() Set hash algorithm via Icm::set_user_algorithm()

pub fn set_dual_input_buffer(&self, dualbuffer: bool)

Control dual input buffer

Enabling dual input buffering allow for better performance at the cost of higher bandwith requirements on the system bus

pub fn set_ascd(&self, automaticswitch: bool)

Automatic switch to Compare Digest

When activated, after the first Main List pass the ICM controller automatically switches to active monitoring.

CDWBN and WBDIS bits has no effects, to terminate the monitoring a 1 needs to be written to End of Monitoring (RCFG.EOM)

pub fn set_busburden(&self, busburden: u8)

Bus burden control

Set a delay between block transfers, calculated as

2.pow(busburden)

Maximum delay is 32768 cycles

pub fn set_slbdis(&self, disable_secondary_lists: bool)

Secondary List Branching Disable

• If set to false, allow secondary lists
• If set to true, secondary lists are forbidden, NEXT and RNEXT is always considered 0.

pub fn set_eomdis(&self, disable_eom: bool)

End of Monitoring Disable

• If set to false, End of Monitoring is permitter
• If set to true, End of Monitoring is forbidden, the EOM bit in RCFG has no effect.

pub fn set_wbdis(&self, disable_eom: bool)

Write Back Disable

• If set to false, Write Back Operations are permitted
• If set to true, Write Back Operations are forbidden, CDWBN bit is internally set to 1 and cannot be modified by a linked list element. The CDWBN bit of the RCFG structure member has no effect.

pub fn set_urad_int(self)

Set Undefined Register Access Detection interrupt enable

pub fn disable_urad_int(self)

Disable Undefined Register Access Detection interrupt enable

pub fn get_urad_int_mask(&self) -> bool

Get Undefined Register Access Detection interrupt mask

pub fn get_urad_int(&self) -> bool

Get Undefined Register Access Detection interrupt status

pub fn get_urat(&self) -> Uratselect

Get Undefined Register Access Trace

This field is only reset by swrst

pub fn get_interrupt_status(&mut self) -> Interrupt

When reading the interrupt (ISR) register, it is cleared

This might result in unexpected results for example when sequentially trying to determine which interrupt triggered.

This is an alternative, return all the data from the register and parse later with the designated get_[name]_int functions.

pub fn trigger_rehash(&self, bitmask: u8)

Trigger recalculation of memory monitor region specified by the bitmask: 0b0001 = region0 0b0010 = region1 0b0100 = region2 0b1000 = region3 … 0b1111 = all regions