Struct AdcBuilder

pub struct AdcBuilder {
    pub clk_divider: Option<Prescaler>,
    pub sample_clock_cycles: Option<u8>,
    pub accumulation: Accumulation,
    pub vref: Option<Reference>,
}

ADC Configuration Builder

This structure provides configuration of multiple factors which affect the ADC’s sampling characteristics.

The ADC clock is driven by the peripheral clock divided with a divider selected via AdcBuilder::with_clock_divider().

A sample is taken over a number of ADC clock cycles configured by AdcBuilder::with_clock_cycles_per_sample(), and then transmitted to the ADC register 1 clock cycle per bit of resolution - resolution is determined by the accumulation mode selected by AdcBuilder::new().

The ADC can be configured to combine multiple readings in either an average or summed mode (See Accumulation).

The formula for calculating Sample rate (SPS) is shown below, and implemented in a helper method AdcBuilder::calculate_sps():

For single sample

SPS = (GCLK_ADC / clk_divider) / (sample_clock_cycles + bit_width)

For multiple samples ‘n’ (Averaging or Summed)

SPS = (GCLK_ADC / clk_divider) / (n * (sample_clock_cycles + 12))

Fields

clk_divider: Option<Prescaler>

sample_clock_cycles: Option<u8>

accumulation: Accumulation

vref: Option<Reference>

Implementations

impl AdcBuilder

pub fn new(accumulation_method: Accumulation) -> Self

Create a new settings builder

pub fn with_clock_divider(self, div: Prescaler) -> Self

This setting adjusts the ADC clock frequency by dividing the input clock for the ADC.

Example:

• Input clock 48MHz, div 32 => ADC Clock is 1.5MHz

pub fn with_vref(self, reference: Reference) -> Self

Sets the ADC reference voltage source

pub fn with_clock_cycles_per_sample(self, num: u8) -> Self

Sets the number of ADC clock cycles taken to sample a single sample. The higher this number, the longer it will take the ADC to sample each sample. Smaller values will make the ADC perform more samples per second, but there may be more noise in each sample leading to erratic values.

Safety

• This function clamps input value between 1 and 63, to conform to the ADC registers min and max values.

pub fn calculate_sps(&self, clock_freq: u32) -> Result<u32, BuilderError>

Returns a calculated sample rate based on the settings used

pub fn enable<I: AdcInstance>( self, adc: I::Instance, pm: &mut Pm, clock: &AdcClock, ) -> Result<Adc<I>, BuilderError>

Trait Implementations

impl Clone for AdcBuilder

fn clone(&self) -> AdcBuilder

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for AdcBuilder