Expand description
Peripheral access API for ATSAMD11D microcontrollers (generated using svd2rust v0.33.5 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open
.
Re-exports§
pub use self::pac0 as pac1;
pub use self::pac0 as pac2;
pub use self::port as port_iobus;
pub use self::sercom0 as sercom1;
pub use self::sercom0 as sercom2;
pub use self::tc1 as tc2;
Modules§
- Analog Comparators
- Analog Digital Converter
- Digital Analog Converter
- Direct Memory Access Controller
- Device Service Unit
- External Interrupt Controller
- Event System Interface
- Generic Clock Generator
- Common register and bit access and modify traits
- HSB Matrix
- Cortex-M0+ Micro-Trace Buffer
- Non-Volatile Memory Controller
- Peripheral Access Controller 0
- Power Manager
- Port Module
- Real-Time Counter
- Serial Communication Interface 0
- System Control
- Basic Timer Counter 1
- Timer Counter Control
- Universal Serial Bus
- Watchdog Timer
Structs§
- Analog Comparators
- Analog Digital Converter
- Cache and branch predictor maintenance operations
- CPUID
- Core peripherals
- Debug Control Block
- Data Watchpoint and Trace unit
- Digital Analog Converter
- Direct Memory Access Controller
- Device Service Unit
- External Interrupt Controller
- Event System Interface
- Flash Patch and Breakpoint unit
- Generic Clock Generator
- HSB Matrix
- Instrumentation Trace Macrocell
- Memory Protection Unit
- Cortex-M0+ Micro-Trace Buffer
- Nested Vector Interrupt Controller
- Non-Volatile Memory Controller
- Peripheral Access Controller 0
- Peripheral Access Controller 1
- Peripheral Access Controller 2
- All the peripherals.
- Power Manager
- Port Module
- Port Module (IOBUS)
- Real-Time Counter
- System Control Block
- SysTick: System Timer
- Serial Communication Interface 0
- Serial Communication Interface 1
- Serial Communication Interface 2
- System Control
- Trace Port Interface Unit
- Basic Timer Counter 1
- Basic Timer Counter 2
- Timer Counter Control
- Universal Serial Bus
- Watchdog Timer
Enums§
- Enumeration of all the interrupts.
Constants§
- Number available in the NVIC for configuring priority