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#[doc = "Register `INTENCLR` reader"]
pub struct R(crate::R<INTENCLR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<INTENCLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<INTENCLR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `INTENCLR` writer"]
pub struct W(crate::W<INTENCLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<INTENCLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<INTENCLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `HSOF` reader - Host Start Of Frame Interrupt Disable"]
pub struct HSOF_R(crate::FieldReader<bool, bool>);
impl HSOF_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
HSOF_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for HSOF_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `HSOF` writer - Host Start Of Frame Interrupt Disable"]
pub struct HSOF_W<'a> {
w: &'a mut W,
}
impl<'a> HSOF_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u16 & 0x01) << 2);
self.w
}
}
#[doc = "Field `RST` reader - BUS Reset Interrupt Disable"]
pub struct RST_R(crate::FieldReader<bool, bool>);
impl RST_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
RST_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for RST_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `RST` writer - BUS Reset Interrupt Disable"]
pub struct RST_W<'a> {
w: &'a mut W,
}
impl<'a> RST_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u16 & 0x01) << 3);
self.w
}
}
#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Disable"]
pub struct WAKEUP_R(crate::FieldReader<bool, bool>);
impl WAKEUP_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
WAKEUP_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for WAKEUP_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Disable"]
pub struct WAKEUP_W<'a> {
w: &'a mut W,
}
impl<'a> WAKEUP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u16 & 0x01) << 4);
self.w
}
}
#[doc = "Field `DNRSM` reader - DownStream to Device Interrupt Disable"]
pub struct DNRSM_R(crate::FieldReader<bool, bool>);
impl DNRSM_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DNRSM_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DNRSM_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DNRSM` writer - DownStream to Device Interrupt Disable"]
pub struct DNRSM_W<'a> {
w: &'a mut W,
}
impl<'a> DNRSM_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u16 & 0x01) << 5);
self.w
}
}
#[doc = "Field `UPRSM` reader - Upstream Resume from Device Interrupt Disable"]
pub struct UPRSM_R(crate::FieldReader<bool, bool>);
impl UPRSM_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
UPRSM_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for UPRSM_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `UPRSM` writer - Upstream Resume from Device Interrupt Disable"]
pub struct UPRSM_W<'a> {
w: &'a mut W,
}
impl<'a> UPRSM_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u16 & 0x01) << 6);
self.w
}
}
#[doc = "Field `RAMACER` reader - Ram Access Interrupt Disable"]
pub struct RAMACER_R(crate::FieldReader<bool, bool>);
impl RAMACER_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
RAMACER_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for RAMACER_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `RAMACER` writer - Ram Access Interrupt Disable"]
pub struct RAMACER_W<'a> {
w: &'a mut W,
}
impl<'a> RAMACER_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u16 & 0x01) << 7);
self.w
}
}
#[doc = "Field `DCONN` reader - Device Connection Interrupt Disable"]
pub struct DCONN_R(crate::FieldReader<bool, bool>);
impl DCONN_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DCONN_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DCONN_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DCONN` writer - Device Connection Interrupt Disable"]
pub struct DCONN_W<'a> {
w: &'a mut W,
}
impl<'a> DCONN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u16 & 0x01) << 8);
self.w
}
}
#[doc = "Field `DDISC` reader - Device Disconnection Interrupt Disable"]
pub struct DDISC_R(crate::FieldReader<bool, bool>);
impl DDISC_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
DDISC_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for DDISC_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `DDISC` writer - Device Disconnection Interrupt Disable"]
pub struct DDISC_W<'a> {
w: &'a mut W,
}
impl<'a> DDISC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u16 & 0x01) << 9);
self.w
}
}
impl R {
#[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
#[inline(always)]
pub fn hsof(&self) -> HSOF_R {
HSOF_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 3 - BUS Reset Interrupt Disable"]
#[inline(always)]
pub fn rst(&self) -> RST_R {
RST_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 4 - Wake Up Interrupt Disable"]
#[inline(always)]
pub fn wakeup(&self) -> WAKEUP_R {
WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
#[inline(always)]
pub fn dnrsm(&self) -> DNRSM_R {
DNRSM_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
#[inline(always)]
pub fn uprsm(&self) -> UPRSM_R {
UPRSM_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - Ram Access Interrupt Disable"]
#[inline(always)]
pub fn ramacer(&self) -> RAMACER_R {
RAMACER_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 8 - Device Connection Interrupt Disable"]
#[inline(always)]
pub fn dconn(&self) -> DCONN_R {
DCONN_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
#[inline(always)]
pub fn ddisc(&self) -> DDISC_R {
DDISC_R::new(((self.bits >> 9) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
#[inline(always)]
pub fn hsof(&mut self) -> HSOF_W {
HSOF_W { w: self }
}
#[doc = "Bit 3 - BUS Reset Interrupt Disable"]
#[inline(always)]
pub fn rst(&mut self) -> RST_W {
RST_W { w: self }
}
#[doc = "Bit 4 - Wake Up Interrupt Disable"]
#[inline(always)]
pub fn wakeup(&mut self) -> WAKEUP_W {
WAKEUP_W { w: self }
}
#[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
#[inline(always)]
pub fn dnrsm(&mut self) -> DNRSM_W {
DNRSM_W { w: self }
}
#[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
#[inline(always)]
pub fn uprsm(&mut self) -> UPRSM_W {
UPRSM_W { w: self }
}
#[doc = "Bit 7 - Ram Access Interrupt Disable"]
#[inline(always)]
pub fn ramacer(&mut self) -> RAMACER_W {
RAMACER_W { w: self }
}
#[doc = "Bit 8 - Device Connection Interrupt Disable"]
#[inline(always)]
pub fn dconn(&mut self) -> DCONN_W {
DCONN_W { w: self }
}
#[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
#[inline(always)]
pub fn ddisc(&mut self) -> DDISC_W {
DDISC_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "HOST Host Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
pub struct INTENCLR_SPEC;
impl crate::RegisterSpec for INTENCLR_SPEC {
type Ux = u16;
}
#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
impl crate::Readable for INTENCLR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
impl crate::Writable for INTENCLR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets INTENCLR to value 0"]
impl crate::Resettable for INTENCLR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}