atsamd_hal/peripherals/adc/d5x/
pin.rs

1use crate::adc::*;
2use crate::gpio::pin::*;
3use atsamd_hal_macros::hal_cfg;
4
5macro_rules! adc_pins {
6    (
7        $(
8            $( #[$cfg:meta] )?
9            $PinId:ident: ($Adc:ident, $CHAN:literal)
10        ),+
11        $(,)?
12    ) => {
13        crate::paste::item! {
14            $(
15                $( #[$cfg] )?
16                impl AdcPin<$Adc> for Pin<$PinId, AlternateB> {
17                    const CHANNEL: u8 = $CHAN;
18                }
19            )+
20        }
21    };
22}
23
24adc_pins! {
25    #[hal_cfg("pa02")]
26    PA02: (Adc0, 0),
27    #[hal_cfg("pa03")]
28    PA03: (Adc0, 1),
29    #[hal_cfg("pb08")]
30    PB08: (Adc0, 2),
31    #[hal_cfg("pb09")]
32    PB09: (Adc0, 3),
33    #[hal_cfg("pa04")]
34    PA04: (Adc0, 4),
35    #[hal_cfg("pa05")]
36    PA05: (Adc0, 5),
37    #[hal_cfg("pa06")]
38    PA06: (Adc0, 6),
39    #[hal_cfg("pa07")]
40    PA07: (Adc0, 7),
41    #[hal_cfg("pa08")]
42    PA08: (Adc0, 8),
43    #[hal_cfg("pa09")]
44    PA09: (Adc0, 9),
45    #[hal_cfg("pa10")]
46    PA10: (Adc0, 10),
47    #[hal_cfg("pa11")]
48    PA11: (Adc0, 11),
49    #[hal_cfg("pb00")]
50    PB00: (Adc0, 12),
51    #[hal_cfg("pb01")]
52    PB01: (Adc0, 13),
53    #[hal_cfg("pb02")]
54    PB02: (Adc0, 14),
55    #[hal_cfg("pb03")]
56    PB03: (Adc0, 15),
57
58    #[hal_cfg("pb08")]
59    PB08: (Adc1, 0),
60    #[hal_cfg("pb09")]
61    PB09: (Adc1, 1),
62    #[hal_cfg("pa08")]
63    PA08: (Adc1, 2),
64    #[hal_cfg("pa09")]
65    PA09: (Adc1, 3),
66    #[hal_cfg("pc02")]
67    PC02: (Adc1, 4),
68    #[hal_cfg("pc03")]
69    PC03: (Adc1, 5),
70    #[hal_cfg("pb04")]
71    PB04: (Adc1, 6),
72    #[hal_cfg("pb05")]
73    PB05: (Adc1, 7),
74    #[hal_cfg("pb06")]
75    PB06: (Adc1, 8),
76    #[hal_cfg("pb07")]
77    PB07: (Adc1, 9),
78    #[hal_cfg("pc00")]
79    PC00: (Adc1, 10),
80    #[hal_cfg("pc01")]
81    PC01: (Adc1, 11),
82    #[hal_cfg("pc30")]
83    PC30: (Adc1, 12),
84    #[hal_cfg("pc31")]
85    PC31: (Adc1, 13),
86    #[hal_cfg("pd00")]
87    PD00: (Adc1, 14),
88    #[hal_cfg("pd01")]
89    PD01: (Adc1, 15),
90}
atsamd_hal/peripherals/adc/d5x/pin.rs

atsamd_hal/peripherals/adc/d5x/
pin.rs
