Expand description
Direct Memory Access Controller
Re-exports§
pub use self::channel::Channel;
Modules§
- active
- Active Channel and Levels
- baseaddr
- Descriptor Memory Section Base Address
- busych
- Busy Channels
- channel
- Cluster CHANNEL[%s]
- crcchksum
- CRC Checksum
- crcctrl
- CRC Control
- crcdatain
- CRC Data Input
- crcstatus
- CRC Status
- ctrl
- Control
- dbgctrl
- Debug Control
- intpend
- Interrupt Pending
- intstatus
- Interrupt Status
- pendch
- Pending Channels
- prictrl0
- Priority Control 0
- swtrigctrl
- Software Trigger Control
- wrbaddr
- Write-Back Memory Section Base Address
Structs§
- Register
Block - Register block
Type Aliases§
- Active
- ACTIVE (r) register accessor: Active Channel and Levels
- Baseaddr
- BASEADDR (rw) register accessor: Descriptor Memory Section Base Address
- Busych
- BUSYCH (r) register accessor: Busy Channels
- Crcchksum
- CRCCHKSUM (rw) register accessor: CRC Checksum
- Crcctrl
- CRCCTRL (rw) register accessor: CRC Control
- Crcdatain
- CRCDATAIN (rw) register accessor: CRC Data Input
- Crcstatus
- CRCSTATUS (rw) register accessor: CRC Status
- Ctrl
- CTRL (rw) register accessor: Control
- Dbgctrl
- DBGCTRL (rw) register accessor: Debug Control
- Intpend
- INTPEND (rw) register accessor: Interrupt Pending
- Intstatus
- INTSTATUS (r) register accessor: Interrupt Status
- Pendch
- PENDCH (r) register accessor: Pending Channels
- Prictrl0
- PRICTRL0 (rw) register accessor: Priority Control 0
- Swtrigctrl
- SWTRIGCTRL (rw) register accessor: Software Trigger Control
- Wrbaddr
- WRBADDR (rw) register accessor: Write-Back Memory Section Base Address