Expand description
§Async interrupts
This module provides APIs specific to working with interrupts in an async peripheral context.
Asynchronous programming relies on tasks that can be paused and resumed without blocking the entire program. When an async task is waiting for a particular event, such as data from a peripheral, it enters a suspended state. It is crucial that the task is properly woken up when the expected event occurs to resume its execution.
By having peripherals take interrupts, they can signal the occurrence of relevant events, effectively waking up the associated async tasks. This ensures that the async runtime can schedule and resume tasks in a timely manner, providing the responsiveness required in embedded systems.
§Typelevel and enum-level interrupts
There are two main ways of representing interrupts in the HAL: either by
using pac::Interrupt
, where each interrupt is represented as an enum
variant, or by using the typelevel interrupts defined in this module. Each
interrupt source that is usable with async peripherals is declared as a
struct with the same name of the corresponsing pac::Interrupt
variant.
Therefore, two distinct traits are needed to perform basic tasks on
interrupt types:
- Use
Interrupt
when dealing with the typelevel interrupt types defined in this module; - Use
InterruptExt
when dealing with enum-level interrupt types defined inpac
.
Re-exports§
pub use crate::interrupt::*;
Enums§
- DMAC typelevel interrupt.
- EIC typelevel interrupt.
- SERCOM0 typelevel interrupt.
- SERCOM1 typelevel interrupt.
- SERCOM2 typelevel interrupt.
- SERCOM3 typelevel interrupt.
- SERCOM4 typelevel interrupt.
- SERCOM5 typelevel interrupt.
- TC3 typelevel interrupt.
- TC4 typelevel interrupt.
- TC5 typelevel interrupt.
Traits§
- Compile-time assertion that an interrupt has been bound to a handler.
- Interrupt handler.
- Type-level interrupt.
- An interrupt source that may have one or many interrupt bindings.
- Marker trait indicating that an interrupt source has multiple bindings and handlers.
- Marker trait indicating that an interrupt source has one binding and one handler.