[−]Struct itsybitsy_m0::SCB
System Control Block
Methods
impl SCB
pub fn vect_active() -> VectActive
Returns the active exception number
impl SCB
pub fn set_sleepdeep(&mut self)
Set the SLEEPDEEP bit in the SCR register
pub fn clear_sleepdeep(&mut self)
Clear the SLEEPDEEP bit in the SCR register
impl SCB
pub fn system_reset(&mut self) -> !
Initiate a system reset request to reset the MCU
impl SCB
pub fn set_pendsv()
Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt
pub fn is_pendsv_pending() -> bool
Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending
pub fn clear_pendsv()
Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt
pub fn set_pendst()
Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
pub fn is_pendst_pending() -> bool
Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
pub fn clear_pendst()
Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
impl SCB
pub fn get_priority(system_handler: SystemHandler) -> u8
Returns the hardware priority of system_handler
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
pub unsafe fn set_priority(&mut self, system_handler: SystemHandler, prio: u8)
Sets the hardware priority of system_handler
to prio
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On ARMv7-M, the operation is performed in a single, atomic write operation.
Unsafety
Changing priority levels can break priority-based critical sections (see
register::basepri
) and compromise memory safety.
impl SCB
pub fn ptr() -> *const RegisterBlock
Returns a pointer to the register block
Trait Implementations
Auto Trait Implementations
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impl<T, U> TryInto for T where
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